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| author | Ville Syrjälä | 2014-02-25 14:13:40 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2014-06-05 08:52:39 +0200 |
| commit | 54e472ae9632992bfbd0c6fd8c8fc5c88d2bdd1f (patch) | |
| tree | aa99d6db0d20ed0b6659be7e4abadd91511b8b7e /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Flip the sense of AGPBUSY_DIS bit (diff) | |
| download | kernel-qcow2-linux-54e472ae9632992bfbd0c6fd8c8fc5c88d2bdd1f.tar.gz kernel-qcow2-linux-54e472ae9632992bfbd0c6fd8c8fc5c88d2bdd1f.tar.xz kernel-qcow2-linux-54e472ae9632992bfbd0c6fd8c8fc5c88d2bdd1f.zip | |
drm/i915: Enable interrupt-based AGPBUSY# enable on 85x
85x also has a similar AGPBUSY# bit as gen3. Enable it to make
sure vblank interrupts don't get dealyed during C3 state.
There's also another bit which controls whether AGPBUSY# is asserted
based on pending cacheable cycles and interrupts, or just based on
pending commands in the ring and interrupts. Select the cacheable
cycles mode since that seems to be the new way of doing things in
85x, and it does give slightly better C3 residency numbers with
glxgears running.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ab98dac3da73..b124ba4ca7e5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5514,6 +5514,10 @@ static void i85x_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); + + /* interrupts should cause a wake up from C3 */ + I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | + _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); } static void i830_init_clock_gating(struct drm_device *dev) |