diff options
| author | Wayne Boyer | 2015-12-09 21:29:35 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2015-12-10 11:07:24 +0100 |
| commit | 666a45379e2c29bc16e60648e5ad8f6f8b7fa6ce (patch) | |
| tree | 09d6b4e4314fd7826e2eb20a805ed28d4b756589 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Cancel hangcheck before GPU is suspended (diff) | |
| download | kernel-qcow2-linux-666a45379e2c29bc16e60648e5ad8f6f8b7fa6ce.tar.gz kernel-qcow2-linux-666a45379e2c29bc16e60648e5ad8f6f8b7fa6ce.tar.xz kernel-qcow2-linux-666a45379e2c29bc16e60648e5ad8f6f8b7fa6ce.zip | |
drm/i915: Separate cherryview from valleyview
The cherryview device shares many characteristics with the valleyview
device. When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.
This patch changes .is_valleyview to .is_cherryview in the cherryview
device info structure and simplifies the IS_CHERRYVIEW macro.
Then where appropriate, instances of IS_VALLEYVIEW are replaced with
IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
Also add followup patches to fix issues discovered during the first
review. (Ville)
v3: Fix some style issues and one gen check. Remove CRT related changes
as CRT is not supported on CHV. (Imre, Ville)
v4: Make a few more optimizations. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1449692975-14803-1-git-send-email-wayne.boyer@intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9968c6623020..99f2642fd5df 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -291,7 +291,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) struct drm_device *dev = dev_priv->dev; u32 val; - if (IS_VALLEYVIEW(dev)) { + if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); POSTING_READ(FW_BLC_SELF_VLV); dev_priv->wm.vlv.cxsr = enable; @@ -4405,7 +4405,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->rps.hw_lock); if (dev_priv->rps.enabled) { - if (IS_VALLEYVIEW(dev)) + if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) vlv_set_rps_idle(dev_priv); else gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); @@ -4458,7 +4458,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv, void intel_set_rps(struct drm_device *dev, u8 val) { - if (IS_VALLEYVIEW(dev)) + if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) valleyview_set_rps(dev, val); else gen6_set_rps(dev, val); @@ -4502,7 +4502,7 @@ static void valleyview_disable_rps(struct drm_device *dev) static void intel_print_rc6_info(struct drm_device *dev, u32 mode) { - if (IS_VALLEYVIEW(dev)) { + if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) mode = GEN6_RC_CTL_RC6_ENABLE; else |