diff options
| author | Deepak S | 2014-07-10 09:46:24 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-07-11 18:22:00 +0200 |
| commit | 67c3bf6f55a97a0915a0f9ea07278a3073cc9601 (patch) | |
| tree | efed3f9d8cc82c764e60f0401b5f74b30c8cd55b /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs (diff) | |
| download | kernel-qcow2-linux-67c3bf6f55a97a0915a0f9ea07278a3073cc9601.tar.gz kernel-qcow2-linux-67c3bf6f55a97a0915a0f9ea07278a3073cc9601.tar.xz kernel-qcow2-linux-67c3bf6f55a97a0915a0f9ea07278a3073cc9601.zip | |
drm/i915: populate mem_freq/cz_clock for chv
We need mem_freq or cz clock for freq/opcode conversion
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8066ca5e2719..32ccd7a9378d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5700,6 +5700,35 @@ static void valleyview_init_clock_gating(struct drm_device *dev) static void cherryview_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + u32 val; + + mutex_lock(&dev_priv->rps.hw_lock); + val = vlv_punit_read(dev_priv, CCK_FUSE_REG); + mutex_unlock(&dev_priv->rps.hw_lock); + switch ((val >> 2) & 0x7) { + case 0: + case 1: + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200; + dev_priv->mem_freq = 1600; + break; + case 2: + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267; + dev_priv->mem_freq = 1600; + break; + case 3: + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333; + dev_priv->mem_freq = 2000; + break; + case 4: + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320; + dev_priv->mem_freq = 1600; + break; + case 5: + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400; + dev_priv->mem_freq = 1600; + break; + } + DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |