diff options
| author | Matt Roper | 2016-05-12 16:06:10 +0200 |
|---|---|---|
| committer | Matt Roper | 2016-05-13 16:36:04 +0200 |
| commit | 6b6bada7d476b586d85b1f9df43125804877e09f (patch) | |
| tree | c83b9c3ae4ef9be12dca6f7f17b1d9bb84e45e62 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915/gen9: Calculate watermarks during atomic 'check' (v2) (diff) | |
| download | kernel-qcow2-linux-6b6bada7d476b586d85b1f9df43125804877e09f.tar.gz kernel-qcow2-linux-6b6bada7d476b586d85b1f9df43125804877e09f.tar.xz kernel-qcow2-linux-6b6bada7d476b586d85b1f9df43125804877e09f.zip | |
drm/i915/gen9: Reject display updates that exceed wm limitations (v2)
If we can't find any valid level 0 watermark values for the requested
atomic transaction, reject the configuration before we try to start
programming the hardware.
v2:
- Add extra debugging output when we reject level 0 watermarks so that
we can more easily debug how/why they were rejected.
Cc: Lyude Paul <cpaul@redhat.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463061971-19638-17-git-send-email-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f9dff5e2e0e7..fcf925b31575 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3306,7 +3306,22 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if (res_blocks >= ddb_allocation || res_lines > 31) { *enabled = false; - return 0; + + /* + * If there are no valid level 0 watermarks, then we can't + * support this display configuration. + */ + if (level) { + return 0; + } else { + DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n"); + DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n", + to_intel_crtc(cstate->base.crtc)->pipe, + skl_wm_plane_id(to_intel_plane(pstate->plane)), + res_blocks, ddb_allocation, res_lines); + + return -EINVAL; + } } *out_blocks = res_blocks; |