diff options
| author | Jesse Barnes | 2012-06-14 20:04:48 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2012-06-18 18:40:48 +0200 |
| commit | b4ae3f22d238617ca11610b29fde16cf8c0bc6e0 (patch) | |
| tree | b7c2ed53fb17491921f4e2ee46c70ff67190cc71 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: disable RCBP and VDS unit clock gating on SNB and VLV (diff) | |
| download | kernel-qcow2-linux-b4ae3f22d238617ca11610b29fde16cf8c0bc6e0.tar.gz kernel-qcow2-linux-b4ae3f22d238617ca11610b29fde16cf8c0bc6e0.tar.xz kernel-qcow2-linux-b4ae3f22d238617ca11610b29fde16cf8c0bc6e0.zip | |
drm/i915: load boot context at driver init time
According to the bspec for MBCTL:
Driver must set bit in the following scenarios:
- to realod teh h/w boot context every time it gets loaded through OS
- after an FLR clears the register (BIOS won't run afterwards)
References: https://bugs.freedesktop.org/show_bug.cgi?id=50237
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 54c5e53dd415..83c0e226f50c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3363,6 +3363,9 @@ static void gen6_init_clock_gating(struct drm_device *dev) ILK_DPARB_CLK_GATE | ILK_DPFD_CLK_GATE); + I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | + GEN6_MBCTL_ENABLE_BOOT_FETCH); + for_each_pipe(pipe) { I915_WRITE(DSPCNTR(pipe), I915_READ(DSPCNTR(pipe)) | @@ -3441,6 +3444,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) intel_flush_display_plane(dev_priv, pipe); } + I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | + GEN6_MBCTL_ENABLE_BOOT_FETCH); + gen7_setup_fixed_func_scheduler(dev_priv); /* WaDisable4x2SubspanOptimization */ @@ -3484,6 +3490,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); + I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | + GEN6_MBCTL_ENABLE_BOOT_FETCH); + /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock * gating disable must be set. Failure to set it results in |