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| author | Ville Syrjälä | 2015-01-21 18:38:01 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2015-01-27 09:51:10 +0100 |
| commit | da2518f9262c89dd182894b29ba45e3d8c95f65c (patch) | |
| tree | 04d8ebe00a82ca73f1d6ff3790bdb118c8c2baa6 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Change CHV WIZ hashing mode to 16x4 (diff) | |
| download | kernel-qcow2-linux-da2518f9262c89dd182894b29ba45e3d8c95f65c.tar.gz kernel-qcow2-linux-da2518f9262c89dd182894b29ba45e3d8c95f65c.tar.xz kernel-qcow2-linux-da2518f9262c89dd182894b29ba45e3d8c95f65c.zip | |
drm/i915: Change VLV WIZ hashing mode to 16x4
We set the WIZ hashing mode to 16x4 for all the other gen6+
platfotrms, so let's follow suit on VLV.
My VLV is AWOL currently so I didn't test this, but since the results
for all the other platforms agree that 16x4 is the fastest we might
assume the same holds for VLV.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e94371e05016..3e630feb18e4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6230,6 +6230,17 @@ static void valleyview_init_clock_gating(struct drm_device *dev) _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); /* + * BSpec recommends 8x4 when MSAA is used, + * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). + */ + I915_WRITE(GEN7_GT_MODE, + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); + + /* * WaIncreaseL3CreditsForVLVB0:vlv * This is the hardware default actually. */ |