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| author | Damien Lespiau | 2015-05-06 15:36:27 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2015-05-08 13:03:44 +0200 |
| commit | f1d3d34d1740e13f01411d85f53945596488d4c1 (patch) | |
| tree | d87cf731b9e48fe4e094b9281d5d58f7a3d47a3e /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence (diff) | |
| download | kernel-qcow2-linux-f1d3d34d1740e13f01411d85f53945596488d4c1.tar.gz kernel-qcow2-linux-f1d3d34d1740e13f01411d85f53945596488d4c1.tar.xz kernel-qcow2-linux-f1d3d34d1740e13f01411d85f53945596488d4c1.zip | |
drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCS
Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
masked register. Re-oops.
A wonder if went through 2 people while having roughly a bug per line...
The problem was introduced in the original patch:
commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
Author: Damien Lespiau <damien.lespiau@intel.com>
Date: Mon Feb 9 19:33:20 2015 +0000
drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS
v2: Also fix the register write (Ville)
Reported-by: Robert Beckett <robert.beckett@intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Robert Beckett <robert.beckett@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9e3bfff2d845..7006f94b94c1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -88,8 +88,7 @@ static void skl_init_clock_gating(struct drm_device *dev) /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ I915_WRITE(FF_SLICE_CS_CHICKEN2, - I915_READ(FF_SLICE_CS_CHICKEN2) | - GEN9_TSG_BARRIER_ACK_DISABLE); + _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); } if (INTEL_REVID(dev) <= SKL_REVID_E0) |