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| author | Ville Syrjälä | 2014-01-23 15:49:13 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2014-01-25 21:17:03 +0100 |
| commit | fe74c1a54f6781beab830f5bf373fc24f273d088 (patch) | |
| tree | 0f9ef0b7ff590159c09f41c056b928fbb4f759a8 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Use 1/2 compression ratio limit for 16bpp on FBC2 (diff) | |
| download | kernel-qcow2-linux-fe74c1a54f6781beab830f5bf373fc24f273d088.tar.gz kernel-qcow2-linux-fe74c1a54f6781beab830f5bf373fc24f273d088.tar.xz kernel-qcow2-linux-fe74c1a54f6781beab830f5bf373fc24f273d088.zip | |
drm/i915: Actually write the correct bits to DPFC_CONTROL on CTG
We set up all the bits for DPFC_CONTROL but forgot to actually
write them to the register. Oops.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a7af5b4d3eb4..75aceaaace8e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -165,7 +165,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc) I915_WRITE(DPFC_FENCE_YOFF, crtc->y); /* enable it... */ - I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); + I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); } |