diff options
| author | Dhinakaran Pandiyan | 2018-05-11 21:51:41 +0200 |
|---|---|---|
| committer | Jani Nikula | 2018-05-24 15:15:14 +0200 |
| commit | 84bb2916a6835636fe28e8db192c3293f2d4df21 (patch) | |
| tree | 1860c972135085094eca489a315dc6020e6b61c0 /drivers/gpu/drm/i915/intel_psr.c | |
| parent | drm/i915/psr: Avoid DPCD reads when panel does not support PSR (diff) | |
| download | kernel-qcow2-linux-84bb2916a6835636fe28e8db192c3293f2d4df21.tar.gz kernel-qcow2-linux-84bb2916a6835636fe28e8db192c3293f2d4df21.tar.xz kernel-qcow2-linux-84bb2916a6835636fe28e8db192c3293f2d4df21.zip | |
drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
By moving the check from psr_compute_config() to psr_init_dpcd(), we get
to set the dev_priv->psr.sink_support flag only when the panel is
capable of changing power state. An additional benefit is that the check
will be performed only at init time instead of every atomic_check.
This should change the psr_basic IGT failures on HSW to skips.
v2: Return early when SET_POWER_CAPABLE bit is 0 (Jose)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106217
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106346
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180511195145.3829-2-dhinakaran.pandiyan@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_psr.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index f0ff005bc86a..26dbb6097981 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -248,9 +248,13 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) if (!intel_dp->psr_dpcd[0]) return; - DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", intel_dp->psr_dpcd[0]); + + if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { + DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n"); + return; + } dev_priv->psr.sink_support = true; if (INTEL_GEN(dev_priv) >= 9 && @@ -570,11 +574,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { - DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n"); - return; - } - crtc_state->has_psr = true; crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : ""); |