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| author | Chris Wilson | 2012-07-20 13:41:07 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2012-07-25 18:23:55 +0200 |
| commit | 016fd0c1aee31902d82c1ac32312f1cc32298b66 (patch) | |
| tree | f7873b3741fe6aabef0e0a520b03aca16b17d75d /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | drm/i915: Replace the complex flushing logic with simple invalidate/flush all (diff) | |
| download | kernel-qcow2-linux-016fd0c1aee31902d82c1ac32312f1cc32298b66.tar.gz kernel-qcow2-linux-016fd0c1aee31902d82c1ac32312f1cc32298b66.tar.xz kernel-qcow2-linux-016fd0c1aee31902d82c1ac32312f1cc32298b66.zip | |
drm/i915: Clear the pending_gpu_fenced_access flag at the start of execbuffer
Otherwise once we use the buffer with a BLT command on gen2/3, we will
always regard future command submissions as continuing the fenced
access. However, now that we flush/invalidate between every batch we can
drop this pessimism.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions