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| author | David Francis | 2019-02-21 21:20:00 +0100 |
|---|---|---|
| committer | Harry Wentland | 2019-03-05 19:24:33 +0100 |
| commit | 06d7cecdb61115de3b573682a6615b05ae993932 (patch) | |
| tree | 6349e371bfe6dfc74ceb8330261efe1ebb41a0d8 /drivers/gpu/drm/i915/intel_vdsc.c | |
| parent | drm/i915: Move dsc rate params compute into drm (diff) | |
| download | kernel-qcow2-linux-06d7cecdb61115de3b573682a6615b05ae993932.tar.gz kernel-qcow2-linux-06d7cecdb61115de3b573682a6615b05ae993932.tar.xz kernel-qcow2-linux-06d7cecdb61115de3b573682a6615b05ae993932.zip | |
drm/dsc: Add native 420 and 422 support to compute_rc_params
Native 420 and 422 transfer modes are new in DSC1.2
In these modes, each two pixels of a slice are treated as one
pixel, so the slice width is half as large (round down) for
the purposes of calucating the groups per line and chunk size
in bytes
In native 422 mode, each pixel has four components, so the
mux component of a group is larger by one additional mux word
and one additional component
Now that there is native 422 support, the configuration option
previously called enable422 is renamed to simple_422 to avoid
confusion
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190221202001.28430-3-David.Francis@amd.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_vdsc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_vdsc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 2d059ebc9bd0..8c8d96157333 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -368,7 +368,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; /* Gen 11 does not support YCbCr */ - vdsc_cfg->enable422 = false; + vdsc_cfg->simple_422 = false; /* Gen 11 does not support VBR */ vdsc_cfg->vbr_enable = false; vdsc_cfg->block_pred_enable = @@ -495,7 +495,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, pps_val |= DSC_BLOCK_PREDICTION; if (vdsc_cfg->convert_rgb) pps_val |= DSC_COLOR_SPACE_CONVERSION; - if (vdsc_cfg->enable422) + if (vdsc_cfg->simple_422) pps_val |= DSC_422_ENABLE; if (vdsc_cfg->vbr_enable) pps_val |= DSC_VBR_ENABLE; |