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| author | Manasi Navare | 2018-11-28 21:26:23 +0100 |
|---|---|---|
| committer | Manasi Navare | 2018-11-29 21:31:14 +0100 |
| commit | a600622c09ddf7da660ca714d5644ecf270426fc (patch) | |
| tree | e58c920943155996b1c7ed5ae9a1af57c451410d /drivers/gpu/drm/i915/intel_vdsc.c | |
| parent | drm/i915/dp: Configure Display stream splitter registers during DSC enable (diff) | |
| download | kernel-qcow2-linux-a600622c09ddf7da660ca714d5644ecf270426fc.tar.gz kernel-qcow2-linux-a600622c09ddf7da660ca714d5644ecf270426fc.tar.xz kernel-qcow2-linux-a600622c09ddf7da660ca714d5644ecf270426fc.zip | |
drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-12-manasi.d.navare@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_vdsc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_vdsc.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 696cb4b8c9ea..ec7444f0ca12 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -1029,3 +1029,34 @@ void intel_dsc_enable(struct intel_encoder *encoder, I915_WRITE(dss_ctl1_reg, dss_ctl1_val); I915_WRITE(dss_ctl2_reg, dss_ctl2_val); } + +void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + u32 dss_ctl1_val = 0, dss_ctl2_val = 0; + + if (!old_crtc_state->dsc_params.compression_enable) + return; + + if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { + dss_ctl1_reg = DSS_CTL1; + dss_ctl2_reg = DSS_CTL2; + } else { + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); + } + dss_ctl1_val = I915_READ(dss_ctl1_reg); + if (dss_ctl1_val & JOINER_ENABLE) + dss_ctl1_val &= ~JOINER_ENABLE; + I915_WRITE(dss_ctl1_reg, dss_ctl1_val); + + dss_ctl2_val = I915_READ(dss_ctl2_reg); + if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE || + dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE) + dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE | + RIGHT_BRANCH_VDSC_ENABLE); + I915_WRITE(dss_ctl2_reg, dss_ctl2_val); +} |