diff options
| author | Chris Wilson | 2019-04-24 11:51:34 +0200 |
|---|---|---|
| committer | Chris Wilson | 2019-04-24 17:37:20 +0200 |
| commit | 09407579abf55a8f472c221325dda81cca324326 (patch) | |
| tree | 589c5b312642ff44528a76d7fe28ddf3d961cc9a /drivers/gpu/drm/i915/selftests/i915_gem_context.c | |
| parent | drm/i915/icl: Fix clockgating issue when using scalers (diff) | |
| download | kernel-qcow2-linux-09407579abf55a8f472c221325dda81cca324326.tar.gz kernel-qcow2-linux-09407579abf55a8f472c221325dda81cca324326.tar.xz kernel-qcow2-linux-09407579abf55a8f472c221325dda81cca324326.zip | |
drm/i915: Store the default sseu setup on the engine
As we push for better compartmentalisation, it is more convenient to
copy the default sseu configuration from the engine into the derived
logical context, than it is to dig it out from i915->runtime_info.
v2: Use intel_sseu_from_device_info() to describe the converter
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424095134.30249-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/selftests/i915_gem_context.c')
| -rw-r--r-- | drivers/gpu/drm/i915/selftests/i915_gem_context.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 4e1b6efc6b22..e1cb22f03e8e 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -962,8 +962,7 @@ __sseu_finish(struct drm_i915_private *i915, unsigned int expected, struct igt_spinner *spin) { - unsigned int slices = - hweight32(intel_device_default_sseu(i915).slice_mask); + unsigned int slices = hweight32(engine->sseu.slice_mask); u32 rpcs = 0; int ret = 0; @@ -1047,8 +1046,8 @@ __igt_ctx_sseu(struct drm_i915_private *i915, const char *name, unsigned int flags) { - struct intel_sseu default_sseu = intel_device_default_sseu(i915); struct intel_engine_cs *engine = i915->engine[RCS0]; + struct intel_sseu default_sseu = engine->sseu; struct drm_i915_gem_object *obj; struct i915_gem_context *ctx; struct intel_sseu pg_sseu; |