diff options
| author | Ben Skeggs | 2012-07-13 08:49:49 +0200 |
|---|---|---|
| committer | Ben Skeggs | 2012-10-03 05:12:50 +0200 |
| commit | 70ee6f1cd6911098ddd4c11ee21b69dbe51fb3f9 (patch) | |
| tree | 3621a402910b4f73ef132263d5dbce59c6a1beb0 /drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c | |
| parent | drm/nv04-nv40/instmem: remove use of nouveau_gpuobj_new_fake() (diff) | |
| download | kernel-qcow2-linux-70ee6f1cd6911098ddd4c11ee21b69dbe51fb3f9.tar.gz kernel-qcow2-linux-70ee6f1cd6911098ddd4c11ee21b69dbe51fb3f9.tar.xz kernel-qcow2-linux-70ee6f1cd6911098ddd4c11ee21b69dbe51fb3f9.zip | |
drm/nv04-nv40/fifo: remove use of nouveau_gpuobj_new_fake()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c | 29 |
1 files changed, 11 insertions, 18 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c index 9c1083afcd34..0da287caf43f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c @@ -61,7 +61,7 @@ struct nv10_fifo_priv { struct nv10_fifo_chan { struct nouveau_fifo_chan base; - struct nouveau_gpuobj *ramfc; + u32 ramfc; }; static int @@ -78,6 +78,8 @@ nv10_fifo_context_new(struct nouveau_channel *chan, int engine) if (!fctx) return -ENOMEM; + fctx->ramfc = chan->id * 32; + /* map channel control registers */ chan->user = ioremap(pci_resource_start(dev->pdev, 0) + NV03_USER(chan->id), PAGE_SIZE); @@ -87,25 +89,16 @@ nv10_fifo_context_new(struct nouveau_channel *chan, int engine) } /* initialise default fifo context */ - ret = nouveau_gpuobj_new_fake(dev, priv->ramfc->pinst + - chan->id * 32, ~0, 32, - NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc); - if (ret) - goto error; - - nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base); - nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base); - nv_wo32(fctx->ramfc, 0x08, 0x00000000); - nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4); - nv_wo32(fctx->ramfc, 0x10, 0x00000000); - nv_wo32(fctx->ramfc, 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | + nv_wo32(priv->ramfc, fctx->ramfc + 0x00, chan->pushbuf_base); + nv_wo32(priv->ramfc, fctx->ramfc + 0x04, chan->pushbuf_base); + nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->pinst >> 4); + nv_wo32(priv->ramfc, fctx->ramfc + 0x14, + NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | #ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | + NV_PFIFO_CACHE1_BIG_ENDIAN | #endif - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); - nv_wo32(fctx->ramfc, 0x18, 0x00000000); - nv_wo32(fctx->ramfc, 0x1c, 0x00000000); + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); /* enable dma mode on the channel */ spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |