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| author | Ben Skeggs | 2013-07-01 06:48:33 +0200 |
|---|---|---|
| committer | Ben Skeggs | 2013-07-05 05:43:06 +0200 |
| commit | 70f824ac8c369194e9499c59e687c6aa8b1a10c8 (patch) | |
| tree | 67ee00e73a433d2b42d67c6e613d2c9c4ebb1a05 /drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c | |
| parent | drm/nve0-/gr: some new gpc registers can have multiple copies (diff) | |
| download | kernel-qcow2-linux-70f824ac8c369194e9499c59e687c6aa8b1a10c8.tar.gz kernel-qcow2-linux-70f824ac8c369194e9499c59e687c6aa8b1a10c8.tar.xz kernel-qcow2-linux-70f824ac8c369194e9499c59e687c6aa8b1a10c8.zip | |
drm/nvc0-/gr: tpc regs a subset of gpc, add separate list for gpc/unk regs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c index 1c68fb11b889..51fb2687b570 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c @@ -783,7 +783,11 @@ nve4_grctx_init_tpc[] = { { 0x419f70, 1, 0x04, 0x00000000 }, { 0x419f78, 1, 0x04, 0x0000000b }, { 0x419f7c, 1, 0x04, 0x0000027a }, + {} +}; +static struct nvc0_graph_init +nve4_grctx_init_unk[] = { { 0x41be24, 1, 0x04, 0x00000006 }, { 0x41bec0, 1, 0x04, 0x12180000 }, { 0x41bec4, 1, 0x04, 0x00037f7f }, @@ -797,7 +801,6 @@ nve4_grctx_init_tpc[] = { { 0x41bfd0, 1, 0x04, 0x00900103 }, { 0x41bfe0, 1, 0x04, 0x00400001 }, { 0x41bfe4, 1, 0x04, 0x00000000 }, - {} }; @@ -911,11 +914,10 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nv_mask(priv, 0x000260, 0x00000001, 0x00000000); - for (i = 0; oclass->mmio[i]; i++) - nvc0_graph_mmio(priv, oclass->mmio[i]); + for (i = 0; oclass->hub[i]; i++) + nvc0_graph_mmio(priv, oclass->hub[i]); for (i = 0; oclass->gpc[i]; i++) nvc0_graph_mmio(priv, oclass->gpc[i]); - nvc0_graph_mmio(priv, oclass->tpc); nv_wr32(priv, 0x404154, 0x00000000); @@ -964,7 +966,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) } static struct nvc0_graph_init * -nve4_grctx_init_mmio[] = { +nve4_grctx_init_hub[] = { nvc0_grctx_init_base, nve4_grctx_init_unk40xx, nvc0_grctx_init_unk44xx, @@ -985,6 +987,8 @@ struct nvc0_graph_init * nve4_grctx_init_gpc[] = { nve4_grctx_init_gpc_0, nvc0_grctx_init_gpc_1, + nve4_grctx_init_tpc, + nve4_grctx_init_unk, NULL }; @@ -1009,9 +1013,8 @@ nve4_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nve4_grctx_generate_main, .mods = nve4_grctx_generate_mods, - .mmio = nve4_grctx_init_mmio, + .hub = nve4_grctx_init_hub, .gpc = nve4_grctx_init_gpc, - .tpc = nve4_grctx_init_tpc, .icmd = nve4_grctx_init_icmd, .mthd = nve4_grctx_init_mthd, }.base; |