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| author | Ben Skeggs | 2013-07-05 02:26:20 +0200 |
|---|---|---|
| committer | Ben Skeggs | 2013-07-05 05:44:52 +0200 |
| commit | d196e16ebf8bc9489ee3dc41dc5dfd84a70cec18 (patch) | |
| tree | 6dfd266b79ce92b5ec62a7452f2906071e2a6aa4 /drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c | |
| parent | drm/nvd7/devinit: use fermi class, not tesla (diff) | |
| download | kernel-qcow2-linux-d196e16ebf8bc9489ee3dc41dc5dfd84a70cec18.tar.gz kernel-qcow2-linux-d196e16ebf8bc9489ee3dc41dc5dfd84a70cec18.tar.xz kernel-qcow2-linux-d196e16ebf8bc9489ee3dc41dc5dfd84a70cec18.zip | |
drm/nvc0-/gr: factor out yet more unknown magic into versioned functions
NVC1/NVD9 are the only chipsets that should have anything different
happen on them after this. We previously weren't doing these
register modifications, and NVIDIA do.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c index 261a600c8ffb..0b72d7240b0b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c @@ -849,6 +849,17 @@ nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) } void +nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv) +{ + nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); + nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); + nv_mask(priv, 0x41be08, 0x00000004, 0x00000004); + nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); + nv_mask(priv, 0x405800, 0x08000000, 0x08000000); + nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); +} + +void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) { u32 data[6] = {}, data2[2] = {}; @@ -922,13 +933,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nv_wr32(priv, 0x404154, 0x00000000); oclass->mods(priv, info); - - nv_wr32(priv, 0x418c6c, 0x1); - nv_wr32(priv, 0x41980c, 0x10); - nv_wr32(priv, 0x41be08, 0x4); - nv_wr32(priv, 0x4064c0, 0x801a00f0); - nv_wr32(priv, 0x405800, 0xf8000bf); - nv_wr32(priv, 0x419c00, 0xa); + oclass->unkn(priv); nvc0_grctx_generate_tpcid(priv); nvc0_grctx_generate_r406028(priv); @@ -1013,6 +1018,7 @@ nve4_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nve4_grctx_generate_main, .mods = nve4_grctx_generate_mods, + .unkn = nve4_grctx_generate_unkn, .hub = nve4_grctx_init_hub, .gpc = nve4_grctx_init_gpc, .icmd = nve4_grctx_init_icmd, |