drm/nouveau/instmem: completely new implementation, as a subdev module

v2 (Ben Skeggs):
- some fixes for 64KiB PAGE_SIZE
- fix porting issues in (currently unused) nv41/nv44 pciegart code

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

22 files changed, 139 insertions, 187 deletions

diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c
index db3b57369830..4b809319e831 100644
--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c
@@ -25,7 +25,6 @@
 #include "drmP.h"
 #include "nouveau_drv.h"
 #include "nouveau_util.h"
-#include <subdev/vm.h>
 #include <core/ramht.h>
 
 /*XXX: This stub is currently used on NV98+ also, as soon as this becomes
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
index fec52463456a..9150c5ed16c3 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
@@ -26,7 +26,6 @@
 #include "drmP.h"
 #include "nouveau_drv.h"
 #include "nouveau_util.h"
-#include <subdev/vm.h>
 #include <core/ramht.h>
 #include "fuc/nva3.fuc.h"
 
@@ -38,7 +37,6 @@ static int
 nva3_copy_context_new(struct nouveau_channel *chan, int engine)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct nouveau_gpuobj *ramin = chan->ramin;
 	struct nouveau_gpuobj *ctx = NULL;
 	int ret;
@@ -51,14 +49,14 @@ nva3_copy_context_new(struct nouveau_channel *chan, int engine)
 		return ret;
 
 	nv_wo32(ramin, 0xc0, 0x00190000);
-	nv_wo32(ramin, 0xc4, ctx->vinst + ctx->size - 1);
-	nv_wo32(ramin, 0xc8, ctx->vinst);
+	nv_wo32(ramin, 0xc4, ctx->addr + ctx->size - 1);
+	nv_wo32(ramin, 0xc8, ctx->addr);
 	nv_wo32(ramin, 0xcc, 0x00000000);
 	nv_wo32(ramin, 0xd0, 0x00000000);
 	nv_wo32(ramin, 0xd4, 0x00000000);
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
-	atomic_inc(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, 1);
 	chan->engctx[engine] = ctx;
 	return 0;
 }
@@ -84,7 +82,7 @@ nva3_copy_context_del(struct nouveau_channel *chan, int engine)
 	for (i = 0xc0; i <= 0xd4; i += 4)
 		nv_wo32(chan->ramin, i, 0x00000000);
 
-	atomic_dec(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, -1);
 	nouveau_gpuobj_ref(NULL, &ctx);
 	chan->engctx[engine] = ctx;
 }
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
index 926f21c0ebce..f39de5a593d6 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
@@ -26,7 +26,6 @@
 #include "drmP.h"
 #include "nouveau_drv.h"
 #include "nouveau_util.h"
-#include <subdev/vm.h>
 #include <core/ramht.h>
 #include "fuc/nvc0.fuc.h"
 
@@ -49,7 +48,6 @@ nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
 	struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
 	struct nvc0_copy_chan *cctx;
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct nouveau_gpuobj *ramin = chan->ramin;
 	int ret;
 
@@ -62,14 +60,14 @@ nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
 	if (ret)
 		return ret;
 
-	ret = nouveau_gpuobj_map_vm(cctx->mem, NV_MEM_ACCESS_RW, chan->vm,
+	ret = nouveau_gpuobj_map_vm(cctx->mem, chan->vm, NV_MEM_ACCESS_RW,
 				   &cctx->vma);
 	if (ret)
 		return ret;
 
 	nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(cctx->vma.offset));
 	nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(cctx->vma.offset));
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 	return 0;
 }
 
@@ -88,7 +86,7 @@ nvc0_copy_context_del(struct nouveau_channel *chan, int engine)
 	struct drm_device *dev = chan->dev;
 	u32 inst;
 
-	inst  = (chan->ramin->vinst >> 12);
+	inst  = (chan->ramin->addr >> 12);
 	inst |= 0x40000000;
 
 	/* disable fifo access */
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
index 388138946ad9..63051ab0ecca 100644
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
@@ -25,7 +25,6 @@
 #include "drmP.h"
 #include "nouveau_drv.h"
 #include "nouveau_util.h"
-#include <subdev/vm.h>
 #include <core/ramht.h>
 
 struct nv84_crypt_engine {
@@ -36,7 +35,6 @@ static int
 nv84_crypt_context_new(struct nouveau_channel *chan, int engine)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct nouveau_gpuobj *ramin = chan->ramin;
 	struct nouveau_gpuobj *ctx;
 	int ret;
@@ -49,14 +47,14 @@ nv84_crypt_context_new(struct nouveau_channel *chan, int engine)
 		return ret;
 
 	nv_wo32(ramin, 0xa0, 0x00190000);
-	nv_wo32(ramin, 0xa4, ctx->vinst + ctx->size - 1);
-	nv_wo32(ramin, 0xa8, ctx->vinst);
+	nv_wo32(ramin, 0xa4, ctx->addr + ctx->size - 1);
+	nv_wo32(ramin, 0xa8, ctx->addr);
 	nv_wo32(ramin, 0xac, 0);
 	nv_wo32(ramin, 0xb0, 0);
 	nv_wo32(ramin, 0xb4, 0);
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
-	atomic_inc(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, 1);
 	chan->engctx[engine] = ctx;
 	return 0;
 }
@@ -68,7 +66,7 @@ nv84_crypt_context_del(struct nouveau_channel *chan, int engine)
 	struct drm_device *dev = chan->dev;
 	u32 inst;
 
-	inst  = (chan->ramin->vinst >> 12);
+	inst  = (chan->ramin->addr >> 12);
 	inst |= 0x80000000;
 
 	/* mark context as invalid if still on the hardware, not
@@ -84,7 +82,7 @@ nv84_crypt_context_del(struct nouveau_channel *chan, int engine)
 
 	nouveau_gpuobj_ref(NULL, &ctx);
 
-	atomic_dec(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, -1);
 	chan->engctx[engine] = NULL;
 }
 
@@ -93,7 +91,6 @@ nv84_crypt_object_new(struct nouveau_channel *chan, int engine,
 		      u32 handle, u16 class)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct nouveau_gpuobj *obj = NULL;
 	int ret;
 
@@ -104,7 +101,7 @@ nv84_crypt_object_new(struct nouveau_channel *chan, int engine,
 	obj->class  = class;
 
 	nv_wo32(obj, 0x00, class);
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
 	ret = nouveau_ramht_insert(chan, handle, obj);
 	nouveau_gpuobj_ref(NULL, &obj);
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
index 563f60d1ce6e..c9adc1b8a7db 100644
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
@@ -26,7 +26,6 @@
 
 #include "nouveau_drv.h"
 #include "nouveau_util.h"
-#include <subdev/vm.h>
 #include <core/ramht.h>
 
 #include "fuc/nv98.fuc.h"
@@ -43,7 +42,6 @@ static int
 nv98_crypt_context_new(struct nouveau_channel *chan, int engine)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct nv98_crypt_priv *priv = nv_engine(dev, engine);
 	struct nv98_crypt_chan *cctx;
 	int ret;
@@ -52,7 +50,7 @@ nv98_crypt_context_new(struct nouveau_channel *chan, int engine)
 	if (!cctx)
 		return -ENOMEM;
 
-	atomic_inc(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, 1);
 
 	ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |
 				 NVOBJ_FLAG_ZERO_FREE, &cctx->mem);
@@ -60,12 +58,12 @@ nv98_crypt_context_new(struct nouveau_channel *chan, int engine)
 		goto error;
 
 	nv_wo32(chan->ramin, 0xa0, 0x00190000);
-	nv_wo32(chan->ramin, 0xa4, cctx->mem->vinst + cctx->mem->size - 1);
-	nv_wo32(chan->ramin, 0xa8, cctx->mem->vinst);
+	nv_wo32(chan->ramin, 0xa4, cctx->mem->addr + cctx->mem->size - 1);
+	nv_wo32(chan->ramin, 0xa8, cctx->mem->addr);
 	nv_wo32(chan->ramin, 0xac, 0x00000000);
 	nv_wo32(chan->ramin, 0xb0, 0x00000000);
 	nv_wo32(chan->ramin, 0xb4, 0x00000000);
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
 error:
 	if (ret)
@@ -84,7 +82,7 @@ nv98_crypt_context_del(struct nouveau_channel *chan, int engine)
 
 	nouveau_gpuobj_ref(NULL, &cctx->mem);
 
-	atomic_dec(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, -1);
 	chan->engctx[engine] = NULL;
 	kfree(cctx);
 }
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
index ba76cf094a6b..6ab7eb0dd9bb 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
@@ -32,8 +32,6 @@
 #include <core/ramht.h>
 #include "nouveau_software.h"
 
-#include <core/subdev/instmem/nv04.h>
-
 static struct ramfc_desc {
 	unsigned bits:6;
 	unsigned ctxs:5;
@@ -120,7 +118,7 @@ nv04_fifo_context_new(struct nouveau_channel *chan, int engine)
 	/* initialise default fifo context */
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x00, chan->pushbuf_base);
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x04, chan->pushbuf_base);
-	nv_wo32(priv->ramfc, fctx->ramfc + 0x08, chan->pushbuf->pinst >> 4);
+	nv_wo32(priv->ramfc, fctx->ramfc + 0x08, chan->pushbuf->addr >> 4);
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x10,
 			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 			     NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
@@ -203,9 +201,9 @@ nv04_fifo_init(struct drm_device *dev, int engine)
 
 	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 				       ((dev_priv->ramht->bits - 9) << 16) |
-				       (dev_priv->ramht->gpuobj->pinst >> 8));
-	nv_wr32(dev, NV03_PFIFO_RAMRO, priv->ramro->pinst >> 8);
-	nv_wr32(dev, NV03_PFIFO_RAMFC, priv->ramfc->pinst >> 8);
+				       (dev_priv->ramht->gpuobj->addr >> 8));
+	nv_wr32(dev, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
+	nv_wr32(dev, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8);
 
 	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, priv->base.channels);
 
@@ -486,15 +484,14 @@ int
 nv04_fifo_create(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nv04_instmem_priv *imem = dev_priv->engine.instmem.priv;
 	struct nv04_fifo_priv *priv;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
-	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
-	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
+	nouveau_gpuobj_ref(nvimem_ramro(dev), &priv->ramro);
+	nouveau_gpuobj_ref(nvimem_ramfc(dev), &priv->ramfc);
 
 	priv->base.base.destroy = nv04_fifo_destroy;
 	priv->base.base.init = nv04_fifo_init;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
index 0da287caf43f..2d38fa88f9c7 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
@@ -31,8 +31,6 @@
 #include "nouveau_util.h"
 #include <core/ramht.h>
 
-#include <core/subdev/instmem/nv04.h>
-
 static struct ramfc_desc {
 	unsigned bits:6;
 	unsigned ctxs:5;
@@ -91,7 +89,7 @@ nv10_fifo_context_new(struct nouveau_channel *chan, int engine)
 	/* initialise default fifo context */
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x00, chan->pushbuf_base);
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x04, chan->pushbuf_base);
-	nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->pinst >> 4);
+	nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->addr >> 4);
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x14,
 			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 			     NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
@@ -115,15 +113,14 @@ int
 nv10_fifo_create(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nv04_instmem_priv *imem = dev_priv->engine.instmem.priv;
 	struct nv10_fifo_priv *priv;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
-	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
-	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
+	nouveau_gpuobj_ref(nvimem_ramro(dev), &priv->ramro);
+	nouveau_gpuobj_ref(nvimem_ramfc(dev), &priv->ramfc);
 
 	priv->base.base.destroy = nv04_fifo_destroy;
 	priv->base.base.init = nv04_fifo_init;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
index 99b88e0ef452..2f700a15e286 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
@@ -31,8 +31,6 @@
 #include "nouveau_util.h"
 #include <core/ramht.h>
 
-#include <core/subdev/instmem/nv04.h>
-
 static struct ramfc_desc {
 	unsigned bits:6;
 	unsigned ctxs:5;
@@ -96,7 +94,7 @@ nv17_fifo_context_new(struct nouveau_channel *chan, int engine)
 	/* initialise default fifo context */
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x00, chan->pushbuf_base);
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x04, chan->pushbuf_base);
-	nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->pinst >> 4);
+	nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->addr >> 4);
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x14,
 			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 			     NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
@@ -131,10 +129,10 @@ nv17_fifo_init(struct drm_device *dev, int engine)
 
 	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 				       ((dev_priv->ramht->bits - 9) << 16) |
-				       (dev_priv->ramht->gpuobj->pinst >> 8));
-	nv_wr32(dev, NV03_PFIFO_RAMRO, priv->ramro->pinst >> 8);
+				       (dev_priv->ramht->gpuobj->addr >> 8));
+	nv_wr32(dev, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
 	nv_wr32(dev, NV03_PFIFO_RAMFC, 0x00010000 |
-				       priv->ramfc->pinst >> 8);
+				       priv->ramfc->addr >> 8);
 
 	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, priv->base.channels);
 
@@ -157,15 +155,14 @@ int
 nv17_fifo_create(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nv04_instmem_priv *imem = dev_priv->engine.instmem.priv;
 	struct nv17_fifo_priv *priv;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
-	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
-	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
+	nouveau_gpuobj_ref(nvimem_ramro(dev), &priv->ramro);
+	nouveau_gpuobj_ref(nvimem_ramfc(dev), &priv->ramfc);
 
 	priv->base.base.destroy = nv04_fifo_destroy;
 	priv->base.base.init = nv17_fifo_init;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
index df53b9f27208..65a670f92a07 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
@@ -31,8 +31,6 @@
 #include "nouveau_util.h"
 #include <core/ramht.h>
 
-#include <core/subdev/instmem/nv04.h>
-
 static struct ramfc_desc {
 	unsigned bits:6;
 	unsigned ctxs:5;
@@ -104,7 +102,7 @@ nv40_fifo_context_new(struct nouveau_channel *chan, int engine)
 	/* initialise default fifo context */
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x00, chan->pushbuf_base);
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x04, chan->pushbuf_base);
-	nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->pinst >> 4);
+	nv_wo32(priv->ramfc, fctx->ramfc + 0x0c, chan->pushbuf->addr >> 4);
 	nv_wo32(priv->ramfc, fctx->ramfc + 0x18, 0x30000000 |
 			     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 			     NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
@@ -144,8 +142,8 @@ nv40_fifo_init(struct drm_device *dev, int engine)
 
 	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 				       ((dev_priv->ramht->bits - 9) << 16) |
-				       (dev_priv->ramht->gpuobj->pinst >> 8));
-	nv_wr32(dev, NV03_PFIFO_RAMRO, priv->ramro->pinst >> 8);
+				       (dev_priv->ramht->gpuobj->addr >> 8));
+	nv_wr32(dev, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
 
 	switch (dev_priv->chipset) {
 	case 0x47:
@@ -163,7 +161,7 @@ nv40_fifo_init(struct drm_device *dev, int engine)
 	default:
 		nv_wr32(dev, 0x002230, 0x00000000);
 		nv_wr32(dev, 0x002220, ((nvfb_vram_size(dev) - 512 * 1024 +
-					 priv->ramfc->pinst) >> 16) |
+					 priv->ramfc->addr) >> 16) |
 				       0x00030000);
 		break;
 	}
@@ -189,15 +187,14 @@ int
 nv40_fifo_create(struct drm_device *dev)
 {
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nv04_instmem_priv *imem = dev_priv->engine.instmem.priv;
 	struct nv40_fifo_priv *priv;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
-	nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
-	nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
+	nouveau_gpuobj_ref(nvimem_ramro(dev), &priv->ramro);
+	nouveau_gpuobj_ref(nvimem_ramfc(dev), &priv->ramfc);
 
 	priv->base.base.destroy = nv04_fifo_destroy;
 	priv->base.base.init = nv40_fifo_init;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
index 2309871704e7..7b5b1592bf61 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
@@ -29,7 +29,6 @@
 #include "nouveau_drv.h"
 #include <engine/fifo.h>
 #include <core/ramht.h>
-#include <subdev/vm.h>
 
 struct nv50_fifo_priv {
 	struct nouveau_fifo_priv base;
@@ -45,7 +44,6 @@ void
 nv50_fifo_playlist_update(struct drm_device *dev)
 {
 	struct nv50_fifo_priv *priv = nv_engine(dev, NVOBJ_ENGINE_FIFO);
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct nouveau_gpuobj *cur;
 	int i, p;
 
@@ -57,9 +55,9 @@ nv50_fifo_playlist_update(struct drm_device *dev)
 			nv_wo32(cur, p++ * 4, i);
 	}
 
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
-	nv_wr32(dev, 0x0032f4, cur->vinst >> 12);
+	nv_wr32(dev, 0x0032f4, cur->addr >> 12);
 	nv_wr32(dev, 0x0032ec, p);
 	nv_wr32(dev, 0x002500, 0x00000101);
 }
@@ -72,14 +70,14 @@ nv50_fifo_context_new(struct nouveau_channel *chan, int engine)
 	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	u64 ib_offset = chan->pushbuf_base + chan->dma.ib_base * 4;
-	u64 instance = chan->ramin->vinst >> 12;
+	u64 instance = chan->ramin->addr >> 12;
 	unsigned long flags;
 	int ret = 0, i;
 
 	fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
 	if (!fctx)
 		return -ENOMEM;
-	atomic_inc(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, 1);
 
 	chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
 			     NV50_USER(chan->id), PAGE_SIZE);
@@ -93,7 +91,7 @@ nv50_fifo_context_new(struct nouveau_channel *chan, int engine)
 	nv_wo32(chan->ramin, 0x3c, 0x403f6078);
 	nv_wo32(chan->ramin, 0x40, 0x00000000);
 	nv_wo32(chan->ramin, 0x44, 0x01003fff);
-	nv_wo32(chan->ramin, 0x48, chan->pushbuf->cinst >> 4);
+	nv_wo32(chan->ramin, 0x48, chan->pushbuf->node->offset >> 4);
 	nv_wo32(chan->ramin, 0x50, lower_32_bits(ib_offset));
 	nv_wo32(chan->ramin, 0x54, upper_32_bits(ib_offset) |
 				   drm_order(chan->dma.ib_max + 1) << 16);
@@ -102,9 +100,9 @@ nv50_fifo_context_new(struct nouveau_channel *chan, int engine)
 	nv_wo32(chan->ramin, 0x7c, 0x30000001);
 	nv_wo32(chan->ramin, 0x80, ((chan->ramht->bits - 9) << 27) |
 				   (4 << 24) /* SEARCH_FULL */ |
-				   (chan->ramht->gpuobj->cinst >> 4));
+				   (chan->ramht->gpuobj->node->offset >> 4));
 
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
 	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 	nv_wr32(dev, 0x002600 + (chan->id * 4), 0x80000000 | instance);
@@ -141,7 +139,7 @@ nv50_fifo_kickoff(struct nouveau_channel *chan)
 	me = nv_mask(dev, 0x00b860, 0x00000001, 0x00000001);
 
 	/* do the kickoff... */
-	nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
+	nv_wr32(dev, 0x0032fc, chan->ramin->addr >> 12);
 	if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff)) {
 		NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);
 		done = false;
@@ -177,7 +175,7 @@ nv50_fifo_context_del(struct nouveau_channel *chan, int engine)
 		chan->user = NULL;
 	}
 
-	atomic_dec(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, -1);
 	chan->engctx[engine] = NULL;
 	kfree(fctx);
 }
@@ -200,7 +198,7 @@ nv50_fifo_init(struct drm_device *dev, int engine)
 	for (i = 0; i < 128; i++) {
 		struct nouveau_channel *chan = dev_priv->channels.ptr[i];
 		if (chan && chan->engctx[engine])
-			instance = 0x80000000 | chan->ramin->vinst >> 12;
+			instance = 0x80000000 | chan->ramin->addr >> 12;
 		else
 			instance = 0x00000000;
 		nv_wr32(dev, 0x002600 + (i * 4), instance);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
index f505d1ed8866..63a4941e285c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
@@ -29,7 +29,6 @@
 #include "nouveau_drv.h"
 #include <engine/fifo.h>
 #include <core/ramht.h>
-#include <subdev/vm.h>
 
 struct nv84_fifo_priv {
 	struct nouveau_fifo_priv base;
@@ -58,7 +57,7 @@ nv84_fifo_context_new(struct nouveau_channel *chan, int engine)
 	fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
 	if (!fctx)
 		return -ENOMEM;
-	atomic_inc(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, 1);
 
 	chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
 			     NV50_USER(chan->id), PAGE_SIZE);
@@ -72,7 +71,7 @@ nv84_fifo_context_new(struct nouveau_channel *chan, int engine)
 	if (ret)
 		goto error;
 
-	instance = fctx->ramfc->vinst >> 8;
+	instance = fctx->ramfc->addr >> 8;
 
 	ret = nouveau_gpuobj_new(dev, chan, 4096, 1024, 0, &fctx->cache);
 	if (ret)
@@ -81,7 +80,7 @@ nv84_fifo_context_new(struct nouveau_channel *chan, int engine)
 	nv_wo32(fctx->ramfc, 0x3c, 0x403f6078);
 	nv_wo32(fctx->ramfc, 0x40, 0x00000000);
 	nv_wo32(fctx->ramfc, 0x44, 0x01003fff);
-	nv_wo32(fctx->ramfc, 0x48, chan->pushbuf->cinst >> 4);
+	nv_wo32(fctx->ramfc, 0x48, chan->pushbuf->node->offset >> 4);
 	nv_wo32(fctx->ramfc, 0x50, lower_32_bits(ib_offset));
 	nv_wo32(fctx->ramfc, 0x54, upper_32_bits(ib_offset) |
 				   drm_order(chan->dma.ib_max + 1) << 16);
@@ -90,14 +89,14 @@ nv84_fifo_context_new(struct nouveau_channel *chan, int engine)
 	nv_wo32(fctx->ramfc, 0x7c, 0x30000001);
 	nv_wo32(fctx->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 				   (4 << 24) /* SEARCH_FULL */ |
-				   (chan->ramht->gpuobj->cinst >> 4));
-	nv_wo32(fctx->ramfc, 0x88, fctx->cache->vinst >> 10);
-	nv_wo32(fctx->ramfc, 0x98, chan->ramin->vinst >> 12);
+				   (chan->ramht->gpuobj->node->offset >> 4));
+	nv_wo32(fctx->ramfc, 0x88, fctx->cache->addr >> 10);
+	nv_wo32(fctx->ramfc, 0x98, chan->ramin->addr >> 12);
 
 	nv_wo32(chan->ramin, 0x00, chan->id);
-	nv_wo32(chan->ramin, 0x04, fctx->ramfc->vinst >> 8);
+	nv_wo32(chan->ramin, 0x04, fctx->ramfc->addr >> 8);
 
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
 	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 	nv_wr32(dev, 0x002600 + (chan->id * 4), 0x80000000 | instance);
@@ -127,7 +126,7 @@ nv84_fifo_context_del(struct nouveau_channel *chan, int engine)
 	save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
 
 	/* tell any engines on this channel to unload their contexts */
-	nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
+	nv_wr32(dev, 0x0032fc, chan->ramin->addr >> 12);
 	if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff))
 		NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);
 
@@ -145,7 +144,7 @@ nv84_fifo_context_del(struct nouveau_channel *chan, int engine)
 	nouveau_gpuobj_ref(NULL, &fctx->ramfc);
 	nouveau_gpuobj_ref(NULL, &fctx->cache);
 
-	atomic_dec(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, -1);
 	chan->engctx[engine] = NULL;
 	kfree(fctx);
 }
@@ -169,7 +168,7 @@ nv84_fifo_init(struct drm_device *dev, int engine)
 	for (i = 0; i < 128; i++) {
 		struct nouveau_channel *chan = dev_priv->channels.ptr[i];
 		if (chan && (fctx = chan->engctx[engine]))
-			instance = 0x80000000 | fctx->ramfc->vinst >> 8;
+			instance = 0x80000000 | fctx->ramfc->addr >> 8;
 		else
 			instance = 0x00000000;
 		nv_wr32(dev, 0x002600 + (i * 4), instance);
@@ -200,7 +199,7 @@ nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend)
 	for (i = 0; i < priv->base.channels; i++) {
 		struct nouveau_channel *chan = dev_priv->channels.ptr[i];
 		if (chan)
-			nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
+			nv_wr32(dev, 0x0032fc, chan->ramin->addr >> 12);
 		if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff)) {
 			NV_INFO(dev, "PFIFO: channel %d unload timeout\n", i);
 			return -EBUSY;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
index f60221d9235d..6535a999015d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
@@ -48,8 +48,6 @@ struct nvc0_fifo_chan {
 static void
 nvc0_fifo_playlist_update(struct drm_device *dev)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 	struct nvc0_fifo_priv *priv = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 	struct nouveau_gpuobj *cur;
 	int i, p;
@@ -64,9 +62,9 @@ nvc0_fifo_playlist_update(struct drm_device *dev)
 		nv_wo32(cur, p + 4, 0x00000004);
 		p += 8;
 	}
-	pinstmem->flush(dev);
+	nvimem_flush(dev);
 
-	nv_wr32(dev, 0x002270, cur->vinst >> 12);
+	nv_wr32(dev, 0x002270, cur->addr >> 12);
 	nv_wr32(dev, 0x002274, 0x01f00000 | (p >> 3));
 	if (!nv_wait(dev, 0x00227c, 0x00100000, 0x00000000))
 		NV_ERROR(dev, "PFIFO - playlist update failed\n");
@@ -76,11 +74,9 @@ static int
 nvc0_fifo_context_new(struct nouveau_channel *chan, int engine)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 	struct nvc0_fifo_priv *priv = nv_engine(dev, engine);
 	struct nvc0_fifo_chan *fctx;
-	u64 usermem = priv->user.mem->vinst + chan->id * 0x1000;
+	u64 usermem = priv->user.mem->addr + chan->id * 0x1000;
 	u64 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
 	int ret, i;
 
@@ -115,10 +111,10 @@ nvc0_fifo_context_new(struct nouveau_channel *chan, int engine)
 	nv_wo32(chan->ramin, 0xb8, 0xf8000000);
 	nv_wo32(chan->ramin, 0xf8, 0x10003080); /* 0x002310 */
 	nv_wo32(chan->ramin, 0xfc, 0x10000010); /* 0x002350 */
-	pinstmem->flush(dev);
+	nvimem_flush(dev);
 
 	nv_wr32(dev, 0x003000 + (chan->id * 8), 0xc0000000 |
-						(chan->ramin->vinst >> 12));
+						(chan->ramin->addr >> 12));
 	nv_wr32(dev, 0x003004 + (chan->id * 8), 0x001f0001);
 	nvc0_fifo_playlist_update(dev);
 
@@ -198,7 +194,7 @@ nvc0_fifo_init(struct drm_device *dev, int engine)
 			continue;
 
 		nv_wr32(dev, 0x003000 + (i * 8), 0xc0000000 |
-						 (chan->ramin->vinst >> 12));
+						 (chan->ramin->addr >> 12));
 		nv_wr32(dev, 0x003004 + (i * 8), 0x001f0001);
 	}
 	nvc0_fifo_playlist_update(dev);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index 1c06bde1bccf..461fbf62492d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -55,8 +55,6 @@ struct nve0_fifo_chan {
 static void
 nve0_fifo_playlist_update(struct drm_device *dev, u32 engine)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 	struct nve0_fifo_priv *priv = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 	struct nve0_fifo_engine *peng = &priv->engine[engine];
 	struct nouveau_gpuobj *cur;
@@ -84,9 +82,9 @@ nve0_fifo_playlist_update(struct drm_device *dev, u32 engine)
 		nv_wo32(cur, p + 4, 0x00000000);
 		p += 8;
 	}
-	pinstmem->flush(dev);
+	nvimem_flush(dev);
 
-	nv_wr32(dev, 0x002270, cur->vinst >> 12);
+	nv_wr32(dev, 0x002270, cur->addr >> 12);
 	nv_wr32(dev, 0x002274, (engine << 20) | (p >> 3));
 	if (!nv_wait(dev, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
 		NV_ERROR(dev, "PFIFO: playlist %d update timeout\n", engine);
@@ -96,11 +94,9 @@ static int
 nve0_fifo_context_new(struct nouveau_channel *chan, int engine)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 	struct nve0_fifo_priv *priv = nv_engine(dev, engine);
 	struct nve0_fifo_chan *fctx;
-	u64 usermem = priv->user.mem->vinst + chan->id * 512;
+	u64 usermem = priv->user.mem->addr + chan->id * 512;
 	u64 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
 	int ret = 0, i;
 
@@ -135,10 +131,10 @@ nve0_fifo_context_new(struct nouveau_channel *chan, int engine)
 	nv_wo32(chan->ramin, 0xe8, chan->id);
 	nv_wo32(chan->ramin, 0xf8, 0x10003080); /* 0x002310 */
 	nv_wo32(chan->ramin, 0xfc, 0x10000010); /* 0x002350 */
-	pinstmem->flush(dev);
+	nvimem_flush(dev);
 
 	nv_wr32(dev, 0x800000 + (chan->id * 8), 0x80000000 |
-						(chan->ramin->vinst >> 12));
+						(chan->ramin->addr >> 12));
 	nv_mask(dev, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400);
 	nve0_fifo_playlist_update(dev, fctx->engine);
 	nv_mask(dev, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400);
@@ -207,7 +203,7 @@ nve0_fifo_init(struct drm_device *dev, int engine)
 			continue;
 
 		nv_wr32(dev, 0x800000 + (i * 8), 0x80000000 |
-						 (chan->ramin->vinst >> 12));
+						 (chan->ramin->addr >> 12));
 		nv_mask(dev, 0x800004 + (i * 8), 0x00000400, 0x00000400);
 		nve0_fifo_playlist_update(dev, fctx->engine);
 		nv_mask(dev, 0x800004 + (i * 8), 0x00000400, 0x00000400);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
index dd31156e3029..0d874b8b18e5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
@@ -52,7 +52,7 @@ nv20_graph_unload_context(struct drm_device *dev)
 		return 0;
 	grctx = chan->engctx[NVOBJ_ENGINE_GR];
 
-	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, grctx->pinst >> 4);
+	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, grctx->addr >> 4);
 	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
 		     NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
 
@@ -437,7 +437,7 @@ nv20_graph_context_new(struct nouveau_channel *chan, int engine)
 	/* CTX_USER */
 	nv_wo32(grctx, pgraph->grctx_user, (chan->id << 24) | 0x1);
 
-	nv_wo32(pgraph->ctxtab, chan->id * 4, grctx->pinst >> 4);
+	nv_wo32(pgraph->ctxtab, chan->id * 4, grctx->addr >> 4);
 	chan->engctx[engine] = grctx;
 	return 0;
 }
@@ -505,7 +505,7 @@ nv20_graph_init(struct drm_device *dev, int engine)
 	nv_wr32(dev, NV03_PMC_ENABLE,
 		nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PGRAPH);
 
-	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
+	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->addr >> 4);
 
 	nv20_graph_rdi(dev);
 
@@ -592,7 +592,7 @@ nv30_graph_init(struct drm_device *dev, int engine)
 	nv_wr32(dev, NV03_PMC_ENABLE,
 		nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PGRAPH);
 
-	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
+	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->addr >> 4);
 
 	nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 	nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
index ab3af6d15381..466d21514b2c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
@@ -52,16 +52,16 @@ nv40_graph_context_new(struct nouveau_channel *chan, int engine)
 
 	/* Initialise default context values */
 	nv40_grctx_fill(dev, grctx);
-	nv_wo32(grctx, 0, grctx->vinst);
+	nv_wo32(grctx, 0, grctx->addr);
 
 	/* init grctx pointer in ramfc, and on PFIFO if channel is
 	 * already active there
 	 */
 	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
-	nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
+	nv_wo32(chan->ramfc, 0x38, grctx->addr >> 4);
 	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
 	if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
-		nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
+		nv_wr32(dev, 0x0032e0, grctx->addr >> 4);
 	nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
 	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
@@ -75,7 +75,7 @@ nv40_graph_context_del(struct nouveau_channel *chan, int engine)
 	struct nouveau_gpuobj *grctx = chan->engctx[engine];
 	struct drm_device *dev = chan->dev;
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	u32 inst = 0x01000000 | (grctx->pinst >> 4);
+	u32 inst = 0x01000000 | (grctx->addr >> 4);
 	unsigned long flags;
 
 	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
@@ -357,7 +357,7 @@ nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
 			continue;
 		grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
 
-		if (grctx && grctx->pinst == inst)
+		if (grctx && grctx->addr == inst)
 			break;
 	}
 	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index b2e9ad4dda06..28932c4662e9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -30,7 +30,6 @@
 #include <engine/fifo.h>
 #include <core/ramht.h>
 #include "nouveau_dma.h"
-#include <subdev/vm.h>
 #include "nv50_evo.h"
 
 struct nv50_graph_engine {
@@ -155,18 +154,18 @@ nv50_graph_context_new(struct nouveau_channel *chan, int engine)
 
 	hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 	nv_wo32(ramin, hdr + 0x00, 0x00190002);
-	nv_wo32(ramin, hdr + 0x04, grctx->vinst + grctx->size - 1);
-	nv_wo32(ramin, hdr + 0x08, grctx->vinst);
+	nv_wo32(ramin, hdr + 0x04, grctx->addr + grctx->size - 1);
+	nv_wo32(ramin, hdr + 0x08, grctx->addr);
 	nv_wo32(ramin, hdr + 0x0c, 0);
 	nv_wo32(ramin, hdr + 0x10, 0);
 	nv_wo32(ramin, hdr + 0x14, 0x00010000);
 
 	nv50_grctx_fill(dev, grctx);
-	nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12);
+	nv_wo32(grctx, 0x00000, chan->ramin->addr >> 12);
 
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
-	atomic_inc(&chan->vm->engref[NVOBJ_ENGINE_GR]);
+	nvvm_engref(chan->vm, engine, 1);
 	chan->engctx[NVOBJ_ENGINE_GR] = grctx;
 	return 0;
 }
@@ -181,9 +180,9 @@ nv50_graph_context_del(struct nouveau_channel *chan, int engine)
 
 	for (i = hdr; i < hdr + 24; i += 4)
 		nv_wo32(chan->ramin, i, 0);
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
-	atomic_dec(&chan->vm->engref[engine]);
+	nvvm_engref(chan->vm, engine, -1);
 	nouveau_gpuobj_ref(NULL, &grctx);
 	chan->engctx[engine] = NULL;
 }
@@ -193,7 +192,6 @@ nv50_graph_object_new(struct nouveau_channel *chan, int engine,
 		      u32 handle, u16 class)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct nouveau_gpuobj *obj = NULL;
 	int ret;
 
@@ -207,7 +205,7 @@ nv50_graph_object_new(struct nouveau_channel *chan, int engine,
 	nv_wo32(obj, 0x04, 0x00000000);
 	nv_wo32(obj, 0x08, 0x00000000);
 	nv_wo32(obj, 0x0c, 0x00000000);
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
 	ret = nouveau_ramht_insert(chan, handle, obj);
 	nouveau_gpuobj_ref(NULL, &obj);
@@ -723,7 +721,7 @@ nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
 		if (!chan || !chan->ramin)
 			continue;
 
-		if (inst == chan->ramin->vinst)
+		if (inst == chan->ramin->addr)
 			break;
 	}
 	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index 8d6eb89b8117..b741b038f0fd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -65,7 +65,7 @@ nvc0_graph_load_context(struct nouveau_channel *chan)
 	struct drm_device *dev = chan->dev;
 
 	nv_wr32(dev, 0x409840, 0x00000030);
-	nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
+	nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->addr >> 12);
 	nv_wr32(dev, 0x409504, 0x00000003);
 	if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
 		NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
@@ -90,7 +90,6 @@ nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
 static int
 nvc0_graph_construct_context(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
 	struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
 	struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
 	struct drm_device *dev = chan->dev;
@@ -103,7 +102,7 @@ nvc0_graph_construct_context(struct nouveau_channel *chan)
 
 	if (!nouveau_ctxfw) {
 		nv_wr32(dev, 0x409840, 0x80000000);
-		nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
+		nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->addr >> 12);
 		nv_wr32(dev, 0x409504, 0x00000001);
 		if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 			NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n");
@@ -118,7 +117,7 @@ nvc0_graph_construct_context(struct nouveau_channel *chan)
 		nv_wo32(grch->grctx, 0x20, 0);
 		nv_wo32(grch->grctx, 0x28, 0);
 		nv_wo32(grch->grctx, 0x2c, 0);
-		dev_priv->engine.instmem.flush(dev);
+		nvimem_flush(dev);
 	}
 
 	ret = nvc0_grctx_generate(chan);
@@ -127,7 +126,7 @@ nvc0_graph_construct_context(struct nouveau_channel *chan)
 
 	if (!nouveau_ctxfw) {
 		nv_wr32(dev, 0x409840, 0x80000000);
-		nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
+		nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->addr >> 12);
 		nv_wr32(dev, 0x409504, 0x00000002);
 		if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 			NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n");
@@ -136,7 +135,7 @@ nvc0_graph_construct_context(struct nouveau_channel *chan)
 			goto err;
 		}
 	} else {
-		ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
+		ret = nvc0_graph_unload_context_to(dev, chan->ramin->addr);
 		if (ret)
 			goto err;
 	}
@@ -165,8 +164,8 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 	if (ret)
 		return ret;
 
-	ret = nouveau_gpuobj_map_vm(grch->unk408004, NV_MEM_ACCESS_RW |
-				    NV_MEM_ACCESS_SYS, chan->vm,
+	ret = nouveau_gpuobj_map_vm(grch->unk408004, chan->vm,
+				    NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
 				    &grch->unk408004_vma);
 	if (ret)
 		return ret;
@@ -175,8 +174,8 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 	if (ret)
 		return ret;
 
-	ret = nouveau_gpuobj_map_vm(grch->unk40800c, NV_MEM_ACCESS_RW |
-				    NV_MEM_ACCESS_SYS, chan->vm,
+	ret = nouveau_gpuobj_map_vm(grch->unk40800c, chan->vm,
+				    NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
 				    &grch->unk40800c_vma);
 	if (ret)
 		return ret;
@@ -186,8 +185,8 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 	if (ret)
 		return ret;
 
-	ret = nouveau_gpuobj_map_vm(grch->unk418810, NV_MEM_ACCESS_RW,
-				    chan->vm, &grch->unk418810_vma);
+	ret = nouveau_gpuobj_map_vm(grch->unk418810, chan->vm,
+				    NV_MEM_ACCESS_RW, &grch->unk418810_vma);
 	if (ret)
 		return ret;
 
@@ -195,9 +194,8 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 	if (ret)
 		return ret;
 
-	ret = nouveau_gpuobj_map_vm(grch->mmio, NV_MEM_ACCESS_RW |
-				    NV_MEM_ACCESS_SYS, chan->vm,
-				    &grch->mmio_vma);
+	ret = nouveau_gpuobj_map_vm(grch->mmio, chan->vm, NV_MEM_ACCESS_RW |
+				    NV_MEM_ACCESS_SYS, &grch->mmio_vma);
 	if (ret)
 		return ret;
 
@@ -268,8 +266,6 @@ static int
 nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 	struct nvc0_graph_priv *priv = nv_engine(dev, engine);
 	struct nvc0_graph_chan *grch;
 	struct nouveau_gpuobj *grctx;
@@ -285,9 +281,8 @@ nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
 	if (ret)
 		goto error;
 
-	ret = nouveau_gpuobj_map_vm(grch->grctx, NV_MEM_ACCESS_RW |
-				    NV_MEM_ACCESS_SYS, chan->vm,
-				    &grch->grctx_vma);
+	ret = nouveau_gpuobj_map_vm(grch->grctx, chan->vm, NV_MEM_ACCESS_RW |
+				    NV_MEM_ACCESS_SYS, &grch->grctx_vma);
 	if (ret)
 		return ret;
 
@@ -299,7 +294,7 @@ nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
 
 	nv_wo32(chan->ramin, 0x0210, lower_32_bits(grch->grctx_vma.offset) | 4);
 	nv_wo32(chan->ramin, 0x0214, upper_32_bits(grch->grctx_vma.offset));
-	pinstmem->flush(dev);
+	nvimem_flush(dev);
 
 	if (!priv->grctx_vals) {
 		ret = nvc0_graph_construct_context(chan);
@@ -324,7 +319,7 @@ nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
 		nv_wo32(grctx, 0x28, 0);
 		nv_wo32(grctx, 0x2c, 0);
 	}
-	pinstmem->flush(dev);
+	nvimem_flush(dev);
 	return 0;
 
 error:
@@ -373,8 +368,8 @@ nvc0_graph_init_obj418880(struct drm_device *dev)
 	nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
 	for (i = 0; i < 4; i++)
 		nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
-	nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
-	nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
+	nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
+	nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
 }
 
 static void
@@ -662,7 +657,7 @@ nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
 		if (!chan || !chan->ramin)
 			continue;
 
-		if (inst == chan->ramin->vinst)
+		if (inst == chan->ramin->addr)
 			break;
 	}
 	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
index 5f671a21b8bb..47bda63ddbcd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
@@ -63,7 +63,7 @@ nve0_graph_load_context(struct nouveau_channel *chan)
 	struct drm_device *dev = chan->dev;
 
 	nv_wr32(dev, 0x409840, 0x00000030);
-	nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
+	nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->addr >> 12);
 	nv_wr32(dev, 0x409504, 0x00000003);
 	if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
 		NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
@@ -88,7 +88,6 @@ nve0_graph_unload_context_to(struct drm_device *dev, u64 chan)
 static int
 nve0_graph_construct_context(struct nouveau_channel *chan)
 {
-	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
 	struct nve0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
 	struct nve0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
 	struct drm_device *dev = chan->dev;
@@ -105,13 +104,13 @@ nve0_graph_construct_context(struct nouveau_channel *chan)
 	nv_wo32(grch->grctx, 0x20, 0);
 	nv_wo32(grch->grctx, 0x28, 0);
 	nv_wo32(grch->grctx, 0x2c, 0);
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
 	ret = nve0_grctx_generate(chan);
 	if (ret)
 		goto err;
 
-	ret = nve0_graph_unload_context_to(dev, chan->ramin->vinst);
+	ret = nve0_graph_unload_context_to(dev, chan->ramin->addr);
 	if (ret)
 		goto err;
 
@@ -141,8 +140,8 @@ nve0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 	if (ret)
 		return ret;
 
-	ret = nouveau_gpuobj_map_vm(grch->unk408004, NV_MEM_ACCESS_RW |
-				    NV_MEM_ACCESS_SYS, chan->vm,
+	ret = nouveau_gpuobj_map_vm(grch->unk408004, chan->vm,
+				    NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
 				    &grch->unk408004_vma);
 	if (ret)
 		return ret;
@@ -151,8 +150,8 @@ nve0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 	if (ret)
 		return ret;
 
-	ret = nouveau_gpuobj_map_vm(grch->unk40800c, NV_MEM_ACCESS_RW |
-				    NV_MEM_ACCESS_SYS, chan->vm,
+	ret = nouveau_gpuobj_map_vm(grch->unk40800c, chan->vm,
+				    NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
 				    &grch->unk40800c_vma);
 	if (ret)
 		return ret;
@@ -162,8 +161,8 @@ nve0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 	if (ret)
 		return ret;
 
-	ret = nouveau_gpuobj_map_vm(grch->unk418810, NV_MEM_ACCESS_RW,
-				    chan->vm, &grch->unk418810_vma);
+	ret = nouveau_gpuobj_map_vm(grch->unk418810, chan->vm,
+				    NV_MEM_ACCESS_RW, &grch->unk418810_vma);
 	if (ret)
 		return ret;
 
@@ -171,8 +170,8 @@ nve0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 	if (ret)
 		return ret;
 
-	ret = nouveau_gpuobj_map_vm(grch->mmio, NV_MEM_ACCESS_RW |
-				    NV_MEM_ACCESS_SYS, chan->vm,
+	ret = nouveau_gpuobj_map_vm(grch->mmio, chan->vm,
+				    NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
 				    &grch->mmio_vma);
 	if (ret)
 		return ret;
@@ -221,8 +220,6 @@ static int
 nve0_graph_context_new(struct nouveau_channel *chan, int engine)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
-	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 	struct nve0_graph_priv *priv = nv_engine(dev, engine);
 	struct nve0_graph_chan *grch;
 	struct nouveau_gpuobj *grctx;
@@ -238,9 +235,8 @@ nve0_graph_context_new(struct nouveau_channel *chan, int engine)
 	if (ret)
 		goto error;
 
-	ret = nouveau_gpuobj_map_vm(grch->grctx, NV_MEM_ACCESS_RW |
-				    NV_MEM_ACCESS_SYS, chan->vm,
-				    &grch->grctx_vma);
+	ret = nouveau_gpuobj_map_vm(grch->grctx, chan->vm, NV_MEM_ACCESS_RW |
+				    NV_MEM_ACCESS_SYS, &grch->grctx_vma);
 	if (ret)
 		return ret;
 
@@ -252,7 +248,7 @@ nve0_graph_context_new(struct nouveau_channel *chan, int engine)
 
 	nv_wo32(chan->ramin, 0x0210, lower_32_bits(grch->grctx_vma.offset) | 4);
 	nv_wo32(chan->ramin, 0x0214, upper_32_bits(grch->grctx_vma.offset));
-	pinstmem->flush(dev);
+	nvimem_flush(dev);
 
 	if (!priv->grctx_vals) {
 		ret = nve0_graph_construct_context(chan);
@@ -272,7 +268,7 @@ nve0_graph_context_new(struct nouveau_channel *chan, int engine)
 	nv_wo32(grctx, 0x28, 0);
 	nv_wo32(grctx, 0x2c, 0);
 
-	pinstmem->flush(dev);
+	nvimem_flush(dev);
 	return 0;
 
 error:
@@ -321,8 +317,8 @@ nve0_graph_init_obj418880(struct drm_device *dev)
 	nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
 	for (i = 0; i < 4; i++)
 		nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
-	nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
-	nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
+	nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
+	nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
 }
 
 static void
@@ -591,7 +587,7 @@ nve0_graph_isr_chid(struct drm_device *dev, u64 inst)
 		if (!chan || !chan->ramin)
 			continue;
 
-		if (inst == chan->ramin->vinst)
+		if (inst == chan->ramin->addr)
 			break;
 	}
 	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
index eb5455fed1bf..a0258c766850 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
@@ -74,8 +74,8 @@ nv40_mpeg_context_new(struct nouveau_channel *chan, int engine)
 	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
 	if ((nv_rd32(dev, 0x003204) & 0x1f) == chan->id)
-		nv_wr32(dev, 0x00330c, ctx->pinst >> 4);
-	nv_wo32(chan->ramfc, 0x54, ctx->pinst >> 4);
+		nv_wr32(dev, 0x00330c, ctx->addr >> 4);
+	nv_wo32(chan->ramfc, 0x54, ctx->addr >> 4);
 	nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
 	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
@@ -90,7 +90,7 @@ nv40_mpeg_context_del(struct nouveau_channel *chan, int engine)
 	struct nouveau_gpuobj *ctx = chan->engctx[engine];
 	struct drm_device *dev = chan->dev;
 	unsigned long flags;
-	u32 inst = 0x80000000 | (ctx->pinst >> 4);
+	u32 inst = 0x80000000 | (ctx->addr >> 4);
 
 	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 	nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
@@ -224,7 +224,7 @@ nv31_mpeg_isr_chid(struct drm_device *dev, u32 inst)
 			continue;
 
 		ctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_MPEG];
-		if (ctx && ctx->pinst == inst)
+		if (ctx && ctx->addr == inst)
 			break;
 	}
 	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
index 47d37a2f478f..4e3292ed80c1 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
@@ -47,7 +47,6 @@ static int
 nv50_mpeg_context_new(struct nouveau_channel *chan, int engine)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct nouveau_gpuobj *ramin = chan->ramin;
 	struct nouveau_gpuobj *ctx = NULL;
 	int ret;
@@ -60,15 +59,15 @@ nv50_mpeg_context_new(struct nouveau_channel *chan, int engine)
 		return ret;
 
 	nv_wo32(ramin, CTX_PTR(dev, 0x00), 0x80190002);
-	nv_wo32(ramin, CTX_PTR(dev, 0x04), ctx->vinst + ctx->size - 1);
-	nv_wo32(ramin, CTX_PTR(dev, 0x08), ctx->vinst);
+	nv_wo32(ramin, CTX_PTR(dev, 0x04), ctx->addr + ctx->size - 1);
+	nv_wo32(ramin, CTX_PTR(dev, 0x08), ctx->addr);
 	nv_wo32(ramin, CTX_PTR(dev, 0x0c), 0);
 	nv_wo32(ramin, CTX_PTR(dev, 0x10), 0);
 	nv_wo32(ramin, CTX_PTR(dev, 0x14), 0x00010000);
 
 	nv_wo32(ctx, 0x70, 0x00801ec1);
 	nv_wo32(ctx, 0x7c, 0x0000037c);
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
 	chan->engctx[engine] = ctx;
 	return 0;
@@ -93,7 +92,6 @@ nv50_mpeg_object_new(struct nouveau_channel *chan, int engine,
 		     u32 handle, u16 class)
 {
 	struct drm_device *dev = chan->dev;
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	struct nouveau_gpuobj *obj = NULL;
 	int ret;
 
@@ -107,7 +105,7 @@ nv50_mpeg_object_new(struct nouveau_channel *chan, int engine,
 	nv_wo32(obj, 0x04, 0x00000000);
 	nv_wo32(obj, 0x08, 0x00000000);
 	nv_wo32(obj, 0x0c, 0x00000000);
-	dev_priv->engine.instmem.flush(dev);
+	nvimem_flush(dev);
 
 	ret = nouveau_ramht_insert(chan, handle, obj);
 	nouveau_gpuobj_ref(NULL, &obj);
diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c b/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c
index 20d33dcd7f40..384de6deeeea 100644
--- a/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c
+++ b/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c
@@ -25,7 +25,6 @@
 #include "drmP.h"
 #include "nouveau_drv.h"
 #include "nouveau_util.h"
-#include <subdev/vm.h>
 #include <core/ramht.h>
 
 struct nv98_ppp_engine {
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
index eb7e1960dd81..5e164a684aec 100644
--- a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
@@ -25,7 +25,6 @@
 #include "drmP.h"
 #include "nouveau_drv.h"
 #include "nouveau_util.h"
-#include <subdev/vm.h>
 #include <core/ramht.h>
 
 /*XXX: This stub is currently used on NV98+ also, as soon as this becomes