diff options
author | Linus Torvalds | 2014-01-30 05:49:12 +0100 |
---|---|---|
committer | Linus Torvalds | 2014-01-30 05:49:12 +0100 |
commit | 9b0cd304f26b9fca140de15deeac2bf357d1f388 (patch) | |
tree | 03a0d74614865a5b776b2a98a433232013b1d369 /drivers/gpu/drm/nouveau/core/subdev/bios | |
parent | Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma (diff) | |
parent | Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/... (diff) | |
download | kernel-qcow2-linux-9b0cd304f26b9fca140de15deeac2bf357d1f388.tar.gz kernel-qcow2-linux-9b0cd304f26b9fca140de15deeac2bf357d1f388.tar.xz kernel-qcow2-linux-9b0cd304f26b9fca140de15deeac2bf357d1f388.zip |
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie:
"Been a bit busy, first week of kids school, and waiting on other trees
to go in before I could send this, so its a bit later than I'd
normally like.
Highlights:
- core:
timestamp fixes, lots of misc cleanups
- new drivers:
bochs virtual vga
- vmwgfx:
major overhaul for their nextgen virt gpu.
- i915:
runtime D3 on HSW, watermark fixes, power well work, fbc fixes,
bdw is no longer prelim.
- nouveau:
gk110/208 acceleration, more pm groundwork, old overlay support
- radeon:
dpm rework and clockgating for CIK, pci config reset, big endian
fixes
- tegra:
panel support and DSI support, build as module, prime.
- armada, omap, gma500, rcar, exynos, mgag200, cirrus, ast:
fixes
- msm:
hdmi support for mdp5"
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (595 commits)
drm/nouveau: resume display if any later suspend bits fail
drm/nouveau: fix lock unbalance in nouveau_crtc_page_flip
drm/nouveau: implement hooks for needed for drm vblank timestamping support
drm/nouveau/disp: add a method to fetch info needed by drm vblank timestamping
drm/nv50: fill in crtc mode struct members from crtc_mode_fixup
drm/radeon/dce8: workaround for atom BlankCrtc table
drm/radeon/DCE4+: clear bios scratch dpms bit (v2)
drm/radeon: set si_notify_smc_display_change properly
drm/radeon: fix DAC interrupt handling on DCE5+
drm/radeon: clean up active vram sizing
drm/radeon: skip async dma init on r6xx
drm/radeon/runpm: don't runtime suspend non-PX cards
drm/radeon: add ring to fence trace functions
drm/radeon: add missing trace point
drm/radeon: fix VMID use tracking
drm: ast,cirrus,mgag200: use drm_can_sleep
drm/gma500: Lock struct_mutex around cursor updates
drm/i915: Fix the offset issue for the stolen GEM objects
DRM: armada: fix missing DRM_KMS_FB_HELPER select
drm/i915: Decouple GPU error reporting from ring initialisation
...
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/subdev/bios')
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/bios/init.c | 48 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c | 67 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c | 107 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/bios/timing.c | 70 |
4 files changed, 230 insertions, 62 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c index df1b1b423093..de201baeb053 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c @@ -9,6 +9,7 @@ #include <subdev/bios/dp.h> #include <subdev/bios/gpio.h> #include <subdev/bios/init.h> +#include <subdev/bios/ramcfg.h> #include <subdev/devinit.h> #include <subdev/i2c.h> #include <subdev/vga.h> @@ -391,43 +392,14 @@ init_unknown_script(struct nouveau_bios *bios) return 0x0000; } -static u16 -init_ram_restrict_table(struct nvbios_init *init) -{ - struct nouveau_bios *bios = init->bios; - struct bit_entry bit_M; - u16 data = 0x0000; - - if (!bit_entry(bios, 'M', &bit_M)) { - if (bit_M.version == 1 && bit_M.length >= 5) - data = nv_ro16(bios, bit_M.offset + 3); - if (bit_M.version == 2 && bit_M.length >= 3) - data = nv_ro16(bios, bit_M.offset + 1); - } - - if (data == 0x0000) - warn("ram restrict table not found\n"); - return data; -} - static u8 init_ram_restrict_group_count(struct nvbios_init *init) { - struct nouveau_bios *bios = init->bios; - struct bit_entry bit_M; - - if (!bit_entry(bios, 'M', &bit_M)) { - if (bit_M.version == 1 && bit_M.length >= 5) - return nv_ro08(bios, bit_M.offset + 2); - if (bit_M.version == 2 && bit_M.length >= 3) - return nv_ro08(bios, bit_M.offset + 0); - } - - return 0x00; + return nvbios_ramcfg_count(init->bios); } static u8 -init_ram_restrict_strap(struct nvbios_init *init) +init_ram_restrict(struct nvbios_init *init) { /* This appears to be the behaviour of the VBIOS parser, and *is* * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to @@ -438,18 +410,8 @@ init_ram_restrict_strap(struct nvbios_init *init) * in case *not* re-reading the strap causes similar breakage. */ if (!init->ramcfg || init->bios->version.major < 0x70) - init->ramcfg = init_rd32(init, 0x101000); - return (init->ramcfg & 0x00000003c) >> 2; -} - -static u8 -init_ram_restrict(struct nvbios_init *init) -{ - u8 strap = init_ram_restrict_strap(init); - u16 table = init_ram_restrict_table(init); - if (table) - return nv_ro08(init->bios, table + strap); - return 0x00; + init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->bios); + return (init->ramcfg & 0x7fffffff); } static u8 diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c b/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c new file mode 100644 index 000000000000..991aedda999b --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c @@ -0,0 +1,67 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include <subdev/bios.h> +#include <subdev/bios/bit.h> +#include <subdev/bios/ramcfg.h> + +static u8 +nvbios_ramcfg_strap(struct nouveau_bios *bios) +{ + return (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2; +} + +u8 +nvbios_ramcfg_count(struct nouveau_bios *bios) +{ + struct bit_entry bit_M; + + if (!bit_entry(bios, 'M', &bit_M)) { + if (bit_M.version == 1 && bit_M.length >= 5) + return nv_ro08(bios, bit_M.offset + 2); + if (bit_M.version == 2 && bit_M.length >= 3) + return nv_ro08(bios, bit_M.offset + 0); + } + + return 0x00; +} + +u8 +nvbios_ramcfg_index(struct nouveau_bios *bios) +{ + u8 strap = nvbios_ramcfg_strap(bios); + u32 xlat = 0x00000000; + struct bit_entry bit_M; + + if (!bit_entry(bios, 'M', &bit_M)) { + if (bit_M.version == 1 && bit_M.length >= 5) + xlat = nv_ro16(bios, bit_M.offset + 3); + if (bit_M.version == 2 && bit_M.length >= 3) + xlat = nv_ro16(bios, bit_M.offset + 1); + } + + if (xlat) + strap = nv_ro08(bios, xlat + strap); + return strap; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c index 916fa9d302b7..1811b2cb0472 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c @@ -24,11 +24,12 @@ #include <subdev/bios.h> #include <subdev/bios/bit.h> +#include <subdev/bios/ramcfg.h> #include <subdev/bios/rammap.h> -u16 -nvbios_rammap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, - u8 *cnt, u8 *len, u8 *snr, u8 *ssz) +u32 +nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, + u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_P; u16 rammap = 0x0000; @@ -57,12 +58,12 @@ nvbios_rammap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, return 0x0000; } -u16 -nvbios_rammap_entry(struct nouveau_bios *bios, int idx, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +u32 +nvbios_rammapEe(struct nouveau_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; - u16 rammap = nvbios_rammap_table(bios, ver, hdr, cnt, len, &snr, &ssz); + u16 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz); if (rammap && idx < *cnt) { rammap = rammap + *hdr + (idx * (*len + (snr * ssz))); *hdr = *len; @@ -73,16 +74,100 @@ nvbios_rammap_entry(struct nouveau_bios *bios, int idx, return 0x0000; } -u16 -nvbios_rammap_match(struct nouveau_bios *bios, u16 khz, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +u32 +nvbios_rammapEm(struct nouveau_bios *bios, u16 khz, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { int idx = 0; u32 data; - while ((data = nvbios_rammap_entry(bios, idx++, ver, hdr, cnt, len))) { + while ((data = nvbios_rammapEe(bios, idx++, ver, hdr, cnt, len))) { if (khz >= nv_ro16(bios, data + 0x00) && khz <= nv_ro16(bios, data + 0x02)) break; } return data; } + +u32 +nvbios_rammapEp(struct nouveau_bios *bios, u16 khz, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_ramcfg *p) +{ + u32 data = nvbios_rammapEm(bios, khz, ver, hdr, cnt, len); + memset(p, 0x00, sizeof(*p)); + switch (!!data * *ver) { + case 0x11: + p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; + p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2; + p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; + p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2; + break; + default: + data = 0; + break; + } + return data; +} + +u32 +nvbios_rammapSe(struct nouveau_bios *bios, u32 data, + u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, + u8 *ver, u8 *hdr) +{ + if (idx < ecnt) { + data = data + ehdr + (idx * elen); + *ver = ever; + *hdr = elen; + return data; + } + return 0; +} + +u32 +nvbios_rammapSp(struct nouveau_bios *bios, u32 data, + u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, + u8 *ver, u8 *hdr, struct nvbios_ramcfg *p) +{ + data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr); + switch (!!data * *ver) { + case 0x11: + p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0; + p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1; + p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2; + p->ramcfg_11_01_08 = (nv_ro08(bios, data + 0x01) & 0x08) >> 3; + p->ramcfg_11_01_10 = (nv_ro08(bios, data + 0x01) & 0x10) >> 4; + p->ramcfg_11_01_20 = (nv_ro08(bios, data + 0x01) & 0x20) >> 5; + p->ramcfg_11_01_40 = (nv_ro08(bios, data + 0x01) & 0x40) >> 6; + p->ramcfg_11_01_80 = (nv_ro08(bios, data + 0x01) & 0x80) >> 7; + p->ramcfg_11_02_03 = (nv_ro08(bios, data + 0x02) & 0x03) >> 0; + p->ramcfg_11_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2; + p->ramcfg_11_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3; + p->ramcfg_11_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4; + p->ramcfg_11_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; + p->ramcfg_11_02_80 = (nv_ro08(bios, data + 0x02) & 0x80) >> 7; + p->ramcfg_11_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0; + p->ramcfg_11_03_30 = (nv_ro08(bios, data + 0x03) & 0x30) >> 4; + p->ramcfg_11_03_c0 = (nv_ro08(bios, data + 0x03) & 0xc0) >> 6; + p->ramcfg_11_03_f0 = (nv_ro08(bios, data + 0x03) & 0xf0) >> 4; + p->ramcfg_11_04 = (nv_ro08(bios, data + 0x04) & 0xff) >> 0; + p->ramcfg_11_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0; + p->ramcfg_11_07_02 = (nv_ro08(bios, data + 0x07) & 0x02) >> 1; + p->ramcfg_11_07_04 = (nv_ro08(bios, data + 0x07) & 0x04) >> 2; + p->ramcfg_11_07_08 = (nv_ro08(bios, data + 0x07) & 0x08) >> 3; + p->ramcfg_11_07_10 = (nv_ro08(bios, data + 0x07) & 0x10) >> 4; + p->ramcfg_11_07_40 = (nv_ro08(bios, data + 0x07) & 0x40) >> 6; + p->ramcfg_11_07_80 = (nv_ro08(bios, data + 0x07) & 0x80) >> 7; + p->ramcfg_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; + p->ramcfg_11_08_02 = (nv_ro08(bios, data + 0x08) & 0x02) >> 1; + p->ramcfg_11_08_04 = (nv_ro08(bios, data + 0x08) & 0x04) >> 2; + p->ramcfg_11_08_08 = (nv_ro08(bios, data + 0x08) & 0x08) >> 3; + p->ramcfg_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; + p->ramcfg_11_08_20 = (nv_ro08(bios, data + 0x08) & 0x20) >> 5; + p->ramcfg_11_09 = (nv_ro08(bios, data + 0x09) & 0xff) >> 0; + break; + default: + data = 0; + break; + } + return data; +} diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c index 151c2d6aaee8..350d44ab2ba2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c @@ -24,11 +24,12 @@ #include <subdev/bios.h> #include <subdev/bios/bit.h> +#include <subdev/bios/ramcfg.h> #include <subdev/bios/timing.h> u16 -nvbios_timing_table(struct nouveau_bios *bios, - u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +nvbios_timingTe(struct nouveau_bios *bios, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_P; u16 timing = 0x0000; @@ -47,11 +48,15 @@ nvbios_timing_table(struct nouveau_bios *bios, *hdr = nv_ro08(bios, timing + 1); *cnt = nv_ro08(bios, timing + 2); *len = nv_ro08(bios, timing + 3); + *snr = 0; + *ssz = 0; return timing; case 0x20: *hdr = nv_ro08(bios, timing + 1); - *cnt = nv_ro08(bios, timing + 3); + *cnt = nv_ro08(bios, timing + 5); *len = nv_ro08(bios, timing + 2); + *snr = nv_ro08(bios, timing + 4); + *ssz = nv_ro08(bios, timing + 3); return timing; default: break; @@ -63,11 +68,60 @@ nvbios_timing_table(struct nouveau_bios *bios, } u16 -nvbios_timing_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +nvbios_timingEe(struct nouveau_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { - u8 hdr, cnt; - u16 timing = nvbios_timing_table(bios, ver, &hdr, &cnt, len); - if (timing && idx < cnt) - return timing + hdr + (idx * *len); + u8 snr, ssz; + u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); + if (timing && idx < *cnt) { + timing += *hdr + idx * (*len + (snr * ssz)); + *hdr = *len; + *cnt = snr; + *len = ssz; + return timing; + } return 0x0000; } + +u16 +nvbios_timingEp(struct nouveau_bios *bios, int idx, + u8 *ver, u8 *hdr, u8 *cnt, u8 *len, + struct nvbios_ramcfg *p) +{ + u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; + switch (!!data * *ver) { + case 0x20: + p->timing[0] = nv_ro32(bios, data + 0x00); + p->timing[1] = nv_ro32(bios, data + 0x04); + p->timing[2] = nv_ro32(bios, data + 0x08); + p->timing[3] = nv_ro32(bios, data + 0x0c); + p->timing[4] = nv_ro32(bios, data + 0x10); + p->timing[5] = nv_ro32(bios, data + 0x14); + p->timing[6] = nv_ro32(bios, data + 0x18); + p->timing[7] = nv_ro32(bios, data + 0x1c); + p->timing[8] = nv_ro32(bios, data + 0x20); + p->timing[9] = nv_ro32(bios, data + 0x24); + p->timing[10] = nv_ro32(bios, data + 0x28); + p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0; + p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4; + p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6; + p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0; + temp = nv_ro16(bios, data + 0x2c); + p->timing_20_2c_003f = (temp & 0x003f) >> 0; + p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6; + p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0; + p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3; + temp = nv_ro16(bios, data + 0x31); + p->timing_20_31_0007 = (temp & 0x0007) >> 0; + p->timing_20_31_0078 = (temp & 0x0078) >> 3; + p->timing_20_31_0780 = (temp & 0x0780) >> 7; + p->timing_20_31_0800 = (temp & 0x0800) >> 11; + p->timing_20_31_7000 = (temp & 0x7000) >> 12; + p->timing_20_31_8000 = (temp & 0x8000) >> 15; + break; + default: + data = 0; + break; + } + return data; +} |