diff options
| author | Younes Manton | 2011-06-24 07:15:58 +0200 |
|---|---|---|
| committer | Ben Skeggs | 2011-06-27 01:20:21 +0200 |
| commit | 3b40d07d8c4a9dc33ee6e1b4ad1d377309531ffe (patch) | |
| tree | 38cd910b50204feb4393420341593302a2aff2c5 /drivers/gpu/drm/nouveau/nv04_instmem.c | |
| parent | drm/nouveau: fix nouveau_vma object leak (diff) | |
| download | kernel-qcow2-linux-3b40d07d8c4a9dc33ee6e1b4ad1d377309531ffe.tar.gz kernel-qcow2-linux-3b40d07d8c4a9dc33ee6e1b4ad1d377309531ffe.tar.xz kernel-qcow2-linux-3b40d07d8c4a9dc33ee6e1b4ad1d377309531ffe.zip | |
drm/nouveau: Calculate reserved VRAM for PRAMIN value before use.
'drm/nouveau: rework vram init/fini ordering a little' changed
the order of instmem.init() and nouveau_mem_vram_init() which
resulted in using ramin_rsvd_vram before it was calculated and
failing to init any accel on pre-NV50 cards.
Since it's only used on <NV50 just calculate it where it's needed
and leave it as default 0 for NV50.
Signed-off-by: Younes Manton <younes.m@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv04_instmem.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv04_instmem.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv04_instmem.c b/drivers/gpu/drm/nouveau/nv04_instmem.c index ae36bfc84853..e2075dec84a3 100644 --- a/drivers/gpu/drm/nouveau/nv04_instmem.c +++ b/drivers/gpu/drm/nouveau/nv04_instmem.c @@ -28,6 +28,31 @@ int nv04_instmem_init(struct drm_device *dev) /* RAMIN always available */ dev_priv->ramin_available = true; + /* Reserve space at end of VRAM for PRAMIN */ + if (dev_priv->card_type >= NV_40) { + u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8); + u32 rsvd; + + /* estimate grctx size, the magics come from nv40_grctx.c */ + if (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs; + else if (dev_priv->chipset < 0x43) rsvd = 0x4f00 * vs; + else if (nv44_graph_class(dev)) rsvd = 0x4980 * vs; + else rsvd = 0x4a40 * vs; + rsvd += 16 * 1024; + rsvd *= dev_priv->engine.fifo.channels; + + /* pciegart table */ + if (drm_pci_device_is_pcie(dev)) + rsvd += 512 * 1024; + + /* object storage */ + rsvd += 512 * 1024; + + dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096); + } else { + dev_priv->ramin_rsvd_vram = 512 * 1024; + } + /* Setup shared RAMHT */ ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096, NVOBJ_FLAG_ZERO_ALLOC, &ramht); |