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authorBen Skeggs2015-08-21 05:38:31 +0200
committerBen Skeggs2015-08-28 04:40:05 +0200
commit2a89359415da2fc1250b4c205de3c384bd781f54 (patch)
tree793e68d347bb71b1ced15711427aea6c3d96e131 /drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
parentdrm/nouveau/disp/dp: fix some tx_pu mishandling (diff)
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drm/nouveau/disp/dp: gm1xx appears to have same dp lane ordering as gm2xx
Fixes 2-lane DP on Quadro K620. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
index 2982ebf1affd..22443627a086 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
@@ -39,11 +39,14 @@ g94_sor_loff(struct nvkm_output_dp *outp)
return g94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
}
-static inline u32
+u32
g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
{
+ static const u8 gm100[] = { 0, 8, 16, 24 };
static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
- static const u8 g94[] = { 16, 8, 0, 24 };
+ static const u8 g94[] = { 16, 8, 0, 24 };
+ if (nv_device(priv)->chipset >= 0x110)
+ return gm100[lane];
if (nv_device(priv)->chipset == 0xaf)
return mcp89[lane];
return g94[lane];