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| author | Tomi Valkeinen | 2014-09-25 21:24:29 +0200 |
|---|---|---|
| committer | Tomi Valkeinen | 2015-03-24 12:50:55 +0100 |
| commit | 7cb0d6c17b96b8bf3c25de2dfde4fdeb9191f4c3 (patch) | |
| tree | 941dfbd181591b7f3ea22a585d05e8d462b40fbf /drivers/gpu/drm/omapdrm/omap_dmm_priv.h | |
| parent | drm/omap: handle incompatible buffer stride and pixel size (diff) | |
| download | kernel-qcow2-linux-7cb0d6c17b96b8bf3c25de2dfde4fdeb9191f4c3.tar.gz kernel-qcow2-linux-7cb0d6c17b96b8bf3c25de2dfde4fdeb9191f4c3.tar.xz kernel-qcow2-linux-7cb0d6c17b96b8bf3c25de2dfde4fdeb9191f4c3.zip | |
drm/omap: fix TILER on OMAP5
On OMAP5 it is not possible to use TILER buffer with CPU when caching or
write-combining is used. Doing so leads to errors from the memory
manager.
However, on OMAP4, write-combining works fine.
This patch adds platform specific data for the TILER, and a function
tiler_get_cpu_cache_flags() which can be used to get the caching mode to
be used.
Note that without write-combining the use of the TILER buffer with CPU
is unusably slow. It's still good to have it operational for testing
purposes.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/omap_dmm_priv.h')
| -rw-r--r-- | drivers/gpu/drm/omapdrm/omap_dmm_priv.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_priv.h b/drivers/gpu/drm/omapdrm/omap_dmm_priv.h index 58bcd6ae0255..d96660573076 100644 --- a/drivers/gpu/drm/omapdrm/omap_dmm_priv.h +++ b/drivers/gpu/drm/omapdrm/omap_dmm_priv.h @@ -153,6 +153,10 @@ struct refill_engine { struct list_head idle_node; }; +struct dmm_platform_data { + uint32_t cpu_cache_flags; +}; + struct dmm { struct device *dev; void __iomem *base; @@ -183,6 +187,8 @@ struct dmm { /* allocation list and lock */ struct list_head alloc_head; + + const struct dmm_platform_data *plat_data; }; #endif |