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authorBenoit Parrot2016-05-16 23:42:50 +0200
committerTomi Valkeinen2018-03-01 08:18:18 +0100
commit9deb5ad3c47ead2b3c63e44435e9eff0f6f38835 (patch)
tree54b38d34ef5118bd48462cb091351a25ee26b783 /drivers/gpu/drm/omapdrm
parentdrm/omap: dispc: disp_wb_setup to check return code (diff)
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drm/omap: Add pclk setting case when channel is DSS_WB
In dispc_set_ovl_common() we need to initialize pclk to a valid value when we use WB in capture mode (i.e. mem_2_mem is false). Otherwise dispc_ovl_calc_scaling() fails. Signed-off-by: Benoit Parrot <bparrot@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm')
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index f0f729fc4ca2..3ad56b30c90a 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -2590,6 +2590,10 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc,
unsigned long pclk = dispc_plane_pclk_rate(dispc, plane);
unsigned long lclk = dispc_plane_lclk_rate(dispc, plane);
+ /* when setting up WB, dispc_plane_pclk_rate() returns 0 */
+ if (plane == OMAP_DSS_WB)
+ pclk = vm->pixelclock;
+
if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
return -EINVAL;