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| author | Laurent Pinchart | 2014-12-08 23:24:49 +0100 |
|---|---|---|
| committer | Laurent Pinchart | 2014-12-23 11:01:50 +0100 |
| commit | 1b30dbde8596ca8de2497c2a50d5381dfe62ee8c (patch) | |
| tree | 1949b3d8d642ddc371ad0b45a44869147629d56f /drivers/gpu/drm/rcar-du/rcar_du_group.c | |
| parent | drm: rcar-du: Refactor DEFR8 feature (diff) | |
| download | kernel-qcow2-linux-1b30dbde8596ca8de2497c2a50d5381dfe62ee8c.tar.gz kernel-qcow2-linux-1b30dbde8596ca8de2497c2a50d5381dfe62ee8c.tar.xz kernel-qcow2-linux-1b30dbde8596ca8de2497c2a50d5381dfe62ee8c.zip | |
drm: rcar-du: Add support for external pixel clock
The DU uses the module functional clock as the default pixel clock, but
supports using an externally supplied pixel clock instead. Support this
by adding the external pixel clock to the DT bindings, and selecting the
clock automatically at runtime based on the requested mode pixel
frequency.
The input clock pins to DU channels routing is configurable, but
currently hardcoded to connect input clock i to channel i.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'drivers/gpu/drm/rcar-du/rcar_du_group.c')
| -rw-r--r-- | drivers/gpu/drm/rcar-du/rcar_du_group.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 7b6428234252..1bdc0ee0c248 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -66,9 +66,21 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE); rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5); - if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) + if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) { rcar_du_group_setup_defr8(rgrp); + /* Configure input dot clock routing. We currently hardcode the + * configuration to routing DOTCLKINn to DUn. + */ + rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE | + DIDSR_LCDS_DCLKIN(2) | + DIDSR_LCDS_DCLKIN(1) | + DIDSR_LCDS_DCLKIN(0) | + DIDSR_PDCS_CLK(2, 0) | + DIDSR_PDCS_CLK(1, 0) | + DIDSR_PDCS_CLK(0, 0)); + } + /* Use DS1PR and DS2PR to configure planes priorities and connects the * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. */ |