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| author | Chris Wilson | 2019-01-02 17:35:24 +0100 |
|---|---|---|
| committer | Chris Wilson | 2019-01-03 11:40:28 +0100 |
| commit | 476af9c2606354f14272297cea8b98afcb94cd8f (patch) | |
| tree | 20c5456aaeef8007c4c31132aa51cdc9c20fb3f2 /drivers/gpu/drm | |
| parent | drm/i915/selftests: Take a breath during check_partial_mappings() (diff) | |
| download | kernel-qcow2-linux-476af9c2606354f14272297cea8b98afcb94cd8f.tar.gz kernel-qcow2-linux-476af9c2606354f14272297cea8b98afcb94cd8f.tar.xz kernel-qcow2-linux-476af9c2606354f14272297cea8b98afcb94cd8f.zip | |
drm/i915/gen6: Flush RING_IMR changes before changing the global GT IMR
On Baytail, notably, we can still detect missed interrupt syndrome
(where we never spot a completed request). In this case, it can be
alleviated by always keeping the interrupt unmasked, implying that the
interrupt is being lost in the window after modifying the IMR. (This is
the reason we still have the posting reads on enable_irq, if we remove
them we miss interrupts!) Having narrowed the issue down to the IMR,
rather than keeping it always enabled, applying the usual posting
read/flush of the RING_IMR before unmasking the GT IMR also seems to
prevent the missed interrupt. So be it.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190102163524.19353-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8967dcb5f58f..3d5d6b908148 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -974,6 +974,10 @@ gen6_irq_enable(struct intel_engine_cs *engine) I915_WRITE_IMR(engine, ~(engine->irq_enable_mask | engine->irq_keep_mask)); + + /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ + POSTING_READ_FW(RING_IMR(engine->mmio_base)); + gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); } |