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| author | Ville Syrjälä | 2014-05-16 18:40:22 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-05-22 15:06:07 +0200 |
| commit | 56b80e1f0022e34f8f92aee867aa8982889cda00 (patch) | |
| tree | 0306e2ee87e1f0fd138de0df12ea55f3141fc565 /drivers/gpu/drm | |
| parent | drm/i915: Check for FIFO underuns when disabling reporting on gmch platforms (diff) | |
| download | kernel-qcow2-linux-56b80e1f0022e34f8f92aee867aa8982889cda00.tar.gz kernel-qcow2-linux-56b80e1f0022e34f8f92aee867aa8982889cda00.tar.xz kernel-qcow2-linux-56b80e1f0022e34f8f92aee867aa8982889cda00.zip | |
drm/i915: Check for FIFO underruns at the end of modeset on gmch
FIFO underruns don't generate interrupts on gmch platforms, so
if we want to know whether a modeset triggered FIFO underruns we
need to explicitly check for them.
As a modeset on one pipe could cause underruns on other pipes,
check for underruns on all pipes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
[danvet: Fix up merge error, kudos to Ville for noticing it.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 28 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 1 |
3 files changed, 35 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 83ad4b43bcd6..57e86bae8f01 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -306,6 +306,34 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev) return true; } +void i9xx_check_fifo_underruns(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *crtc; + unsigned long flags; + + spin_lock_irqsave(&dev_priv->irq_lock, flags); + + for_each_intel_crtc(dev, crtc) { + u32 reg = PIPESTAT(crtc->pipe); + u32 pipestat; + + if (crtc->cpu_fifo_underrun_disabled) + continue; + + pipestat = I915_READ(reg) & 0xffff0000; + if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) + continue; + + I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); + POSTING_READ(reg); + + DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); + } + + spin_unlock_irqrestore(&dev_priv->irq_lock, flags); +} + static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, enum pipe pipe, bool enable) { diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6c5db7c8caf4..8d960d240611 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4625,6 +4625,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) intel_crtc_enable_planes(crtc); drm_crtc_vblank_on(crtc); + + /* Underruns don't raise interrupts, so check manually. */ + i9xx_check_fifo_underruns(dev); } static void i9xx_set_pll_dividers(struct intel_crtc *crtc) @@ -4704,6 +4707,9 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) intel_crtc_enable_planes(crtc); drm_crtc_vblank_on(crtc); + + /* Underruns don't raise interrupts, so check manually. */ + i9xx_check_fifo_underruns(dev); } static void i9xx_pfit_disable(struct intel_crtc *crtc) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a78eb75411c9..fe2533ba52a9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -680,6 +680,7 @@ void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void intel_runtime_pm_disable_interrupts(struct drm_device *dev); void intel_runtime_pm_restore_interrupts(struct drm_device *dev); int intel_get_crtc_scanline(struct intel_crtc *crtc); +void i9xx_check_fifo_underruns(struct drm_device *dev); /* intel_crt.c */ |