diff options
| author | Mika Kuoppala | 2016-06-07 16:19:13 +0200 |
|---|---|---|
| committer | Mika Kuoppala | 2016-07-15 14:51:27 +0200 |
| commit | 0e51c0bdc0e6503c9c1cf2c41b2f1ae4e9cf9a8b (patch) | |
| tree | ed67f20bfa8ed3a7ee9c86fc710e066c226168ad /drivers/gpu | |
| parent | drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing (diff) | |
| download | kernel-qcow2-linux-0e51c0bdc0e6503c9c1cf2c41b2f1ae4e9cf9a8b.tar.gz kernel-qcow2-linux-0e51c0bdc0e6503c9c1cf2c41b2f1ae4e9cf9a8b.tar.xz kernel-qcow2-linux-0e51c0bdc0e6503c9c1cf2c41b2f1ae4e9cf9a8b.zip | |
drm/i915/gen9: Add WaEnableChickenDCPR
Workaround for display underrun issues with Y & Yf Tiling.
Set this on all gen9 as stated by bspec.
v2: proper workaround name
References: HSD#2136383, BSID#857
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.o/* register 01h */
#define CS4362A_PDN 0x01
#define CS4362A_DAC1_DIS 0x02
#define CS4362A_DAC2_DIS 0x04
#define CS4362A_DAC3_DIS 0x08
#define CS4362A_MCLKDIV 0x20
#define CS4362A_FREEZE 0x40
#define -rw-r--r-- drivers/gpu/drm/i915/i915_reg.h 3
-rw-r--r-- drivers/gpu/drm/i915/intel_pm.c 4
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 349470d0ff1c..87655ac6a39c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6059,6 +6059,9 @@ enum skl_disp_power_wells { #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) +#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) +#define MASK_WAKEMEM (1<<13) + #define SKL_DFSM _MMIO(0x51000) #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3f0f1880d4af..362800ba63a8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -64,6 +64,10 @@ static void gen9_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN8_CONFIG0, I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); + + /* WaEnableChickenDCPR:skl,bxt,kbl */ + I915_WRITE(GEN8_CHICKEN_DCPR_1, + I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); } static void bxt_init_clock_gating(struct drm_device *dev) |