diff options
| author | Tvrtko Ursulin | 2016-06-29 17:09:32 +0200 |
|---|---|---|
| committer | Tvrtko Ursulin | 2016-06-30 18:20:45 +0200 |
| commit | 8d228911ffc08bfaa8224d160df8ca64e9dc8274 (patch) | |
| tree | 5bc61e1019252906a7fe22d937b7420138257524 /drivers/gpu | |
| parent | drm/i915: Consolidate legacy semaphore initialization (diff) | |
| download | kernel-qcow2-linux-8d228911ffc08bfaa8224d160df8ca64e9dc8274.tar.gz kernel-qcow2-linux-8d228911ffc08bfaa8224d160df8ca64e9dc8274.tar.xz kernel-qcow2-linux-8d228911ffc08bfaa8224d160df8ca64e9dc8274.zip | |
drm/i915: Trim some if-else braces
Just a bit of cleanup after the previous refactoring.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1467212972-861-1-git-send-email-tvrtko.ursulin@linux.intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2080668d3630..4d61ea923154 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -3126,20 +3126,18 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) if (IS_GEN6(dev_priv)) engine->write_tail = gen6_bsd_ring_write_tail; engine->flush = gen6_bsd_ring_flush; - if (INTEL_GEN(dev_priv) >= 8) { + if (INTEL_GEN(dev_priv) >= 8) engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; - } else { + else engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; - } } else { engine->mmio_base = BSD_RING_BASE; engine->flush = bsd_ring_flush; - if (IS_GEN5(dev_priv)) { + if (IS_GEN5(dev_priv)) engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; - } else { + else engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; - } } return intel_init_ring_buffer(dev, engine); @@ -3182,12 +3180,11 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) intel_ring_default_vfuncs(dev_priv, engine); engine->flush = gen6_ring_flush; - if (INTEL_GEN(dev_priv) >= 8) { + if (INTEL_GEN(dev_priv) >= 8) engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; - } else { + else engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; - } return intel_init_ring_buffer(dev, engine); } |