diff options
| author | Deepak S | 2016-08-12 15:16:41 +0200 |
|---|---|---|
| committer | Ville Syrjälä | 2017-02-14 22:23:54 +0100 |
| commit | 96676fe3a18e61ee2d67992da537d6b68f45df66 (patch) | |
| tree | ef05c783c654ce32e9dfafac590b2c7c0f44656b /drivers/gpu | |
| parent | drm/i915: Dump more configuration information for DSI (diff) | |
| download | kernel-qcow2-linux-96676fe3a18e61ee2d67992da537d6b68f45df66.tar.gz kernel-qcow2-linux-96676fe3a18e61ee2d67992da537d6b68f45df66.tar.xz kernel-qcow2-linux-96676fe3a18e61ee2d67992da537d6b68f45df66.zip | |
drm/i915/chv: Set min freq to RPn on CHV.
With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
This is not a 1:1 revert of the commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
You can refer to commit 5b5929cbe3f7 ("drm/i915/chv: remove
pre-production hardware workarounds") as the reason for the discrepancy
commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44
Author: Deepak S <deepak.s@linux.intel.com>
Date: Sat May 9 18:15:46 2015 +0530
drm/i915/chv: Set min freq to efficient frequency on chv
v2: Fix inconsistent return type. (Chris)
v3: drop pre-production hw case (Ville)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471007801-86075-1-git-send-email-deepak.s@linux.intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3c13be8985f1..633cb0478b92 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5708,6 +5708,17 @@ static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) return rp1; } +static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv) +{ + u32 val, rpn; + + val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); + rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & + FB_GFX_FREQ_FUSE_MASK); + + return rpn; +} + static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) { u32 val, rp1; @@ -5944,8 +5955,7 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv) intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), dev_priv->rps.rp1_freq); - /* PUnit validated range is only [RPe, RP0] */ - dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), dev_priv->rps.min_freq); |