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| author | Charlene Liu | 2017-07-25 03:41:28 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-09-27 00:15:39 +0200 |
| commit | ee356d8f4fff35510b83aa71299ddc0ccb798d58 (patch) | |
| tree | ccc7f5f9ef9bdc88d854a50e94c07f0b873346d7 /drivers/gpu | |
| parent | drm/amd/display: Roll core_gamma into dc_gamma (diff) | |
| download | kernel-qcow2-linux-ee356d8f4fff35510b83aa71299ddc0ccb798d58.tar.gz kernel-qcow2-linux-ee356d8f4fff35510b83aa71299ddc0ccb798d58.tar.xz kernel-qcow2-linux-ee356d8f4fff35510b83aa71299ddc0ccb798d58.zip | |
drm/amd/display: single PSR display not allow CSTATE sw w/a
Description:
HW issue when all the pipes are off, DCE_allow_cstate is 0.
New sequence : blank OTG only instead of previous OTG_master_en=0)
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_types.h | 3 |
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index e7062069d9a1..fd2ae181cff2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1548,6 +1548,12 @@ bool dc_link_setup_psr(struct dc_link *link, psr_context->psr_level.u32all = 0; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /*skip power down the single pipe since it blocks the cstate*/ + if (ASIC_REV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev)) + psr_context->psr_level.bits.SKIP_SINGLE_OTG_DISABLE = true; +#endif + /* SMU will perform additional powerdown sequence. * For unsupported ASICs, set psr_level flag to skip PSR * static screen notification to SMU. diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index c7539fe36b66..99b893fbcb42 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -539,7 +539,8 @@ union dmcu_psr_level { unsigned int SKIP_SMU_NOTIFICATION:1; unsigned int SKIP_AUTO_STATE_ADVANCE:1; unsigned int DISABLE_PSR_ENTRY_ABORT:1; - unsigned int RESERVED:23; + unsigned int SKIP_SINGLE_OTG_DISABLE:1; + unsigned int RESERVED:22; } bits; unsigned int u32all; }; |