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author | Suzuki K Poulose | 2017-08-02 18:22:13 +0200 |
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committer | Greg Kroah-Hartman | 2017-08-28 16:05:49 +0200 |
commit | ff11f5bc5a42f2cfc9705481eedf1b4d470ade2c (patch) | |
tree | a3d15c9886f66e0d152c5ca60c4546a019e29aab /drivers/hwtracing/coresight/coresight-tmc-etr.c | |
parent | coresight tmc: Detect support for scatter gather (diff) | |
download | kernel-qcow2-linux-ff11f5bc5a42f2cfc9705481eedf1b4d470ade2c.tar.gz kernel-qcow2-linux-ff11f5bc5a42f2cfc9705481eedf1b4d470ade2c.tar.xz kernel-qcow2-linux-ff11f5bc5a42f2cfc9705481eedf1b4d470ade2c.zip |
coresight tmc etr: Detect address width at runtime
TMC in Coresight SoC-600 advertises the AXI address width
in the device configuration register.
Bit 16 - AXIAW_VALID
0 - AXI Address Width not valid
1 - Valid AXI Address width in Bits[23-17]
Bits [23-17] - AXIAW. If AXIAW_VALID = b01 then
0x20 - 32bit AXI address bus
0x28 - 40bit AXI address bus
0x2c - 44bit AXI address bus
0x30 - 48bit AXI address bus
0x34 - 52bit AXI address bus
Use the address bits from the device configuration register, if
available. Otherwise, default to 40bit.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-tmc-etr.c')
0 files changed, 0 insertions, 0 deletions