diff options
| author | Will Deacon | 2013-08-21 14:49:53 +0200 |
|---|---|---|
| committer | Will Deacon | 2013-10-09 15:14:38 +0200 |
| commit | 25724841dfaed05f23a3ddaaaed5c9b61ceea7bd (patch) | |
| tree | 4a9dbaf96ec07f0db4c1c606e088fe14f1f18fb9 /drivers/iommu/arm-smmu.c | |
| parent | iommu/arm-smmu: replace devm_request_and_ioremap by devm_ioremap_resource (diff) | |
| download | kernel-qcow2-linux-25724841dfaed05f23a3ddaaaed5c9b61ceea7bd.tar.gz kernel-qcow2-linux-25724841dfaed05f23a3ddaaaed5c9b61ceea7bd.tar.xz kernel-qcow2-linux-25724841dfaed05f23a3ddaaaed5c9b61ceea7bd.zip | |
iommu/arm-smmu: use relaxed accessors where possible
Apart from fault handling and page table manipulation, we don't care
about memory ordering between SMMU control registers and normal,
cacheable memory, so use the _relaxed I/O accessors wherever possible.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu/arm-smmu.c')
| -rw-r--r-- | drivers/iommu/arm-smmu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index abe83c3757ab..293192150f5a 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -778,7 +778,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) #ifdef __BIG_ENDIAN reg |= SCTLR_E; #endif - writel(reg, cb_base + ARM_SMMU_CB_SCTLR); + writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); } static int arm_smmu_init_domain_context(struct iommu_domain *domain, @@ -1595,7 +1595,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Push the button */ arm_smmu_tlb_sync(smmu); - writel(scr0, gr0_base + ARM_SMMU_GR0_sCR0); + writel_relaxed(scr0, gr0_base + ARM_SMMU_GR0_sCR0); } static int arm_smmu_id_size_to_bits(int size) @@ -1928,7 +1928,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev) free_irq(smmu->irqs[i], smmu); /* Turn the thing off */ - writel(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0); + writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0); return 0; } |