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| author | Will Deacon | 2014-02-06 00:35:47 +0100 |
|---|---|---|
| committer | Will Deacon | 2014-02-24 20:09:46 +0100 |
| commit | 3aa80ea4c90d46ffbe200d05b9ceb997001b36df (patch) | |
| tree | ae640b0a46b3f0590138659df5afe0e5a0d77339 /drivers/iommu/arm-smmu.c | |
| parent | iommu/arm-smmu: clean up use of `flags' in page table handling code (diff) | |
| download | kernel-qcow2-linux-3aa80ea4c90d46ffbe200d05b9ceb997001b36df.tar.gz kernel-qcow2-linux-3aa80ea4c90d46ffbe200d05b9ceb997001b36df.tar.xz kernel-qcow2-linux-3aa80ea4c90d46ffbe200d05b9ceb997001b36df.zip | |
iommu/arm-smmu: provide option to dsb macro when publishing tables
On coherent systems, publishing new page tables to the SMMU walker is
achieved with a dsb instruction. In fact, this can be a dsb(ishst) which
also provides the mandatory barrier option for arm64.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu/arm-smmu.c')
| -rw-r--r-- | drivers/iommu/arm-smmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 83297fe0878d..1da5b41afc31 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -678,7 +678,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, /* Ensure new page tables are visible to the hardware walker */ if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) { - dsb(); + dsb(ishst); } else { /* * If the SMMU can't walk tables in the CPU caches, treat them |