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| author | Philip Rakity | 2011-05-13 07:47:15 +0200 |
|---|---|---|
| committer | Chris Ball | 2011-05-25 05:53:57 +0200 |
| commit | 6322cdd0eb22e016aeced886c2046d115139c962 (patch) | |
| tree | 8ab17b8220413f828b0edaceb1f0964b4ecf7dab /drivers/mmc/host/sdhci.c | |
| parent | mmc: core: clear MMC_PM_KEEP_POWER flag on resume (diff) | |
| download | kernel-qcow2-linux-6322cdd0eb22e016aeced886c2046d115139c962.tar.gz kernel-qcow2-linux-6322cdd0eb22e016aeced886c2046d115139c962.tar.xz kernel-qcow2-linux-6322cdd0eb22e016aeced886c2046d115139c962.zip | |
mmc: sdhci: add hooks for setting UHS in platform specific code
Allow platform specific code to set UHS registers if
implementation requires speciial platform specific handling
Signed-off-by: Philip Rakity <prakity@marvell.com>
Reviewed-by: Arindam Nath <arindam.nath@amd.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc/host/sdhci.c')
| -rw-r--r-- | drivers/mmc/host/sdhci.c | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index fa3301644b15..cc63f5ed2310 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1346,27 +1346,30 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) sdhci_set_clock(host, clock); } - ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); - - /* Select Bus Speed Mode for host */ - ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; - if (ios->timing == MMC_TIMING_UHS_SDR12) - ctrl_2 |= SDHCI_CTRL_UHS_SDR12; - else if (ios->timing == MMC_TIMING_UHS_SDR25) - ctrl_2 |= SDHCI_CTRL_UHS_SDR25; - else if (ios->timing == MMC_TIMING_UHS_SDR50) - ctrl_2 |= SDHCI_CTRL_UHS_SDR50; - else if (ios->timing == MMC_TIMING_UHS_SDR104) - ctrl_2 |= SDHCI_CTRL_UHS_SDR104; - else if (ios->timing == MMC_TIMING_UHS_DDR50) - ctrl_2 |= SDHCI_CTRL_UHS_DDR50; /* Reset SD Clock Enable */ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); clk &= ~SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + if (host->ops->set_uhs_signaling) + host->ops->set_uhs_signaling(host, ios->timing); + else { + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + if (ios->timing == MMC_TIMING_UHS_SDR12) + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + else if (ios->timing == MMC_TIMING_UHS_SDR25) + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + else if (ios->timing == MMC_TIMING_UHS_SDR50) + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + else if (ios->timing == MMC_TIMING_UHS_SDR104) + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + else if (ios->timing == MMC_TIMING_UHS_DDR50) + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } /* Re-enable SD Clock */ clock = host->clock; |