diff options
| author | Huang Shijie | 2014-03-27 03:43:22 +0100 |
|---|---|---|
| committer | Brian Norris | 2014-05-29 01:02:16 +0200 |
| commit | 91f5498ebfb2352ed6b5eb2780adcfe019961565 (patch) | |
| tree | c2eb5107cb99dc328901184b0d60ba36d0c48115 /drivers/mtd/nand/gpmi-nand/gpmi-lib.c | |
| parent | mtd: maps: remove check for CONFIG_MTD_SUPERH_RESERVE (diff) | |
| download | kernel-qcow2-linux-91f5498ebfb2352ed6b5eb2780adcfe019961565.tar.gz kernel-qcow2-linux-91f5498ebfb2352ed6b5eb2780adcfe019961565.tar.xz kernel-qcow2-linux-91f5498ebfb2352ed6b5eb2780adcfe019961565.zip | |
mtd: gpmi: add gpmi support for imx6sx
The gpmi's IP for imx6sx is nearly the same as the gpmi's IP for imx6q,
except the following two new features:
(1) the new BCH contoller has 62-BIT correcting ECC strength
(The BCH for imx6q only has 40-BIT ECC strength).
(2) add the hardware Randomizer support.
This patch does the follow changes:
(1) add a new macro GPMI_IS_MX6SX to represent the imx6sx's gpmi.
(2) add a new macro GPMI_IS_MX6.
We use this macro to initialize the same registers for both
imx6sx and imx6q, and so on.
(3) add a new gpmi_devdata instance, the gpmi_devdata_imx6sx, for
imx6sx.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd/nand/gpmi-nand/gpmi-lib.c')
| -rw-r--r-- | drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index ec4db2a359e5..87e658ce23ef 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -971,7 +971,7 @@ int gpmi_extra_init(struct gpmi_nand_data *this) struct nand_chip *chip = &this->nand; /* Enable the asynchronous EDO feature. */ - if (GPMI_IS_MX6Q(this) && chip->onfi_version) { + if (GPMI_IS_MX6(this) && chip->onfi_version) { int mode = onfi_get_async_timing_mode(chip); /* We only support the timing mode 4 and mode 5. */ @@ -1093,12 +1093,12 @@ int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip) if (GPMI_IS_MX23(this)) { mask = MX23_BM_GPMI_DEBUG_READY0 << chip; reg = readl(r->gpmi_regs + HW_GPMI_DEBUG); - } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6Q(this)) { + } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6(this)) { /* * In the imx6, all the ready/busy pins are bound * together. So we only need to check chip 0. */ - if (GPMI_IS_MX6Q(this)) + if (GPMI_IS_MX6(this)) chip = 0; /* MX28 shares the same R/B register as MX6Q. */ |