diff options
| author | Iyappan Subramanian | 2016-12-02 01:41:42 +0100 |
|---|---|---|
| committer | David S. Miller | 2016-12-03 21:46:50 +0100 |
| commit | bb64fa09ac1b22515dc04d9dec3096da812f758b (patch) | |
| tree | 177cdd95bd76188c87f71069cbd1a62f1200f6a7 /drivers/net/ethernet/apm/xgene/xgene_enet_hw.h | |
| parent | drivers: net: xgene: fix: RSS for non-TCP/UDP (diff) | |
| download | kernel-qcow2-linux-bb64fa09ac1b22515dc04d9dec3096da812f758b.tar.gz kernel-qcow2-linux-bb64fa09ac1b22515dc04d9dec3096da812f758b.tar.xz kernel-qcow2-linux-bb64fa09ac1b22515dc04d9dec3096da812f758b.zip | |
drivers: net: xgene: Add flow control configuration
This patch adds functions to configure mac, when flow control
and pause frame settings change.
Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/apm/xgene/xgene_enet_hw.h')
| -rw-r--r-- | drivers/net/ethernet/apm/xgene/xgene_enet_hw.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h index bd6cb6c43390..7ba649d2573d 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h @@ -170,6 +170,10 @@ enum xgene_enet_rm { #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) #define CFG_CLE_DSTQID0(val) ((val) & GENMASK(11, 0)) #define CFG_CLE_FPSEL0(val) (((val) << 16) & GENMASK(19, 16)) +#define CSR_ECM_CFG_0_ADDR 0x0220 +#define CSR_ECM_CFG_1_ADDR 0x0224 +#define PAUSE_XON_EN BIT(30) +#define MULTI_DPF_AUTOCTRL BIT(28) #define CFG_CLE_NXTFPSEL0(val) (((val) << 20) & GENMASK(23, 20)) #define ICM_CONFIG0_REG_0_ADDR 0x0400 #define ICM_CONFIG2_REG_0_ADDR 0x0410 @@ -198,6 +202,8 @@ enum xgene_enet_rm { #define SOFT_RESET1 BIT(31) #define TX_EN BIT(0) #define RX_EN BIT(2) +#define TX_FLOW_EN BIT(4) +#define RX_FLOW_EN BIT(5) #define ENET_LHD_MODE BIT(25) #define ENET_GHD_MODE BIT(26) #define FULL_DUPLEX2 BIT(0) |