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author | Yuval Mintz | 2012-12-02 05:05:50 +0100 |
---|---|---|
committer | David S. Miller | 2012-12-03 02:22:59 +0100 |
commit | 7964211d3891d0271c5fc8087cd49c018b30476d (patch) | |
tree | 5ad794185d65be12b12e2a28b2229901dea0e8d6 /drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h | |
parent | bnx2x: Correct advertised speed/duplex (diff) | |
download | kernel-qcow2-linux-7964211d3891d0271c5fc8087cd49c018b30476d.tar.gz kernel-qcow2-linux-7964211d3891d0271c5fc8087cd49c018b30476d.tar.xz kernel-qcow2-linux-7964211d3891d0271c5fc8087cd49c018b30476d.zip |
bnx2x: nvram enables dropless flow control
It is now possible to enable dropless flow control via nvram.
Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h')
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h index 9a51d4970ad5..3369a50ac6b4 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h @@ -500,7 +500,15 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ u32 e3_cmn_pin_cfg1; /* 0x170 */ #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 - u32 reserved0[7]; /* 0x174 */ + + /* pause on host ring */ + u32 generic_features; /* 0x174 */ + #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 + #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 + #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 + #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 + + u32 reserved0[6]; /* 0x178 */ u32 aeu_int_mask; /* 0x190 */ @@ -1518,12 +1526,13 @@ enum mf_cfg_afex_vlan_mode { /* This structure is not applicable and should not be accessed on 57711 */ struct func_ext_cfg { u32 func_cfg; - #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF + #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F #define MACP_FUNC_CFG_FLAGS_SHIFT 0 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 + #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 u32 iscsi_mac_addr_upper; u32 iscsi_mac_addr_lower; |