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| author | David S. Miller | 2014-09-19 22:27:13 +0200 |
|---|---|---|
| committer | David S. Miller | 2014-09-19 22:27:13 +0200 |
| commit | 77f4f6220a98f4f3eb08be10230d7e8c604aa2b8 (patch) | |
| tree | 76f44de1599ba25217e24f3905732010260e0df2 /drivers/net/ethernet/broadcom/genet/bcmgenet.c | |
| parent | net: add alloc_skb_with_frags() helper (diff) | |
| parent | net: phy: bcm7xxx: utilize PHY revision in config_init (diff) | |
| download | kernel-qcow2-linux-77f4f6220a98f4f3eb08be10230d7e8c604aa2b8.tar.gz kernel-qcow2-linux-77f4f6220a98f4f3eb08be10230d7e8c604aa2b8.tar.xz kernel-qcow2-linux-77f4f6220a98f4f3eb08be10230d7e8c604aa2b8.zip | |
Merge branch 'fec-next'
Florian Fainelli says:
====================
net: phy: Broadcom BCM7xxx PHY workaround update
This patch sets the change to of_phy_connect() that you have seen before,
this time with the full context of why it is useful and applicable here.
Due to some design decision, the internal PHY on Broadcom BCM7xxx chips
is not entirely self contained and does not report its internal revision
through MII_PHYSID2, that is left to external PHY designs.
This forces us to get the PHY revision from the GENET and SF2 switch drivers
because those two peripherals integrate such a PHY and do contain the PHY
revision in their registers.
The approach taken here is hopefully easy to extend to similar needs for
other chips/ as well.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/genet/bcmgenet.c')
| -rw-r--r-- | drivers/net/ethernet/broadcom/genet/bcmgenet.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c index 3f9d4de8173c..a12c65604f9d 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c @@ -2432,6 +2432,13 @@ static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, major, (reg >> 16) & 0x0f, reg & 0xffff); + /* Store the integrated PHY revision for the MDIO probing function + * to pass this information to the PHY driver. The PHY driver expects + * to find the PHY major revision in bits 15:8 while the GENET register + * stores that information in bits 7:0, account for that. + */ + priv->gphy_rev = (reg & 0xffff) << 8; + #ifdef CONFIG_PHYS_ADDR_T_64BIT if (!(params->flags & GENET_HAS_40BITS)) pr_warn("GENET does not support 40-bits PA\n"); |