diff options
| author | Raghu Vatsavayi | 2016-08-31 20:03:29 +0200 |
|---|---|---|
| committer | David S. Miller | 2016-08-31 23:12:48 +0200 |
| commit | c0eab5b3580af67196b6b4a59db8ed44fc5ed46c (patch) | |
| tree | d34669bf7a4e9a4b4311e2cf58c48c9d02ff599f /drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c | |
| parent | liquidio: MSIX support for CN23XX (diff) | |
| download | kernel-qcow2-linux-c0eab5b3580af67196b6b4a59db8ed44fc5ed46c.tar.gz kernel-qcow2-linux-c0eab5b3580af67196b6b4a59db8ed44fc5ed46c.tar.xz kernel-qcow2-linux-c0eab5b3580af67196b6b4a59db8ed44fc5ed46c.zip | |
liquidio: CN23XX firmware download
Add firmware download support for cn23xx device.
Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com>
Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com>
Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com>
Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c')
| -rw-r--r-- | drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c b/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c index 2e78101c3653..2d812064731a 100644 --- a/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c +++ b/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c @@ -214,6 +214,37 @@ void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct) CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_CNT_INT))); } +static int cn23xx_pf_soft_reset(struct octeon_device *oct) +{ + octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF); + + dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: BIST enabled for CN23XX soft reset\n", + oct->octeon_id); + + octeon_write_csr64(oct, CN23XX_SLI_SCRATCH1, 0x1234ULL); + + /* Initiate chip-wide soft reset */ + lio_pci_readq(oct, CN23XX_RST_SOFT_RST); + lio_pci_writeq(oct, 1, CN23XX_RST_SOFT_RST); + + /* Wait for 100ms as Octeon resets. */ + mdelay(100); + + if (octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1) == 0x1234ULL) { + dev_err(&oct->pci_dev->dev, "OCTEON[%d]: Soft reset failed\n", + oct->octeon_id); + return 1; + } + + dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Reset completed\n", + oct->octeon_id); + + /* restore the reset value*/ + octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF); + + return 0; +} + static void cn23xx_enable_error_reporting(struct octeon_device *oct) { u32 regval; @@ -1030,6 +1061,7 @@ int setup_cn23xx_octeon_pf_device(struct octeon_device *oct) oct->fn_list.process_interrupt_regs = cn23xx_interrupt_handler; oct->fn_list.msix_interrupt_handler = cn23xx_pf_msix_interrupt_handler; + oct->fn_list.soft_reset = cn23xx_pf_soft_reset; oct->fn_list.setup_device_regs = cn23xx_setup_pf_device_regs; oct->fn_list.enable_interrupt = cn23xx_enable_pf_interrupt; @@ -1129,3 +1161,11 @@ void cn23xx_dump_iq_regs(struct octeon_device *oct) CVM_CAST64(octeon_read_csr64( oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)))); } + +int cn23xx_fw_loaded(struct octeon_device *oct) +{ + u64 val; + + val = octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1); + return (val >> 1) & 1ULL; +} |