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authorHariprasad Shenai2015-12-23 18:17:17 +0100
committerDavid S. Miller2015-12-24 04:34:45 +0100
commit115b56af88b538147cf241d0f75a370a73009ed9 (patch)
treebbc8c7a3d543e55886ae01de4a7484e69e4a34ba /drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
parentcxgb4: Update correct encoding of SGE Ingress DMA States for T6 adapter (diff)
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cxgb4: Update mps_tcam output to include T6 fields
In T6, MPS classification has a 512 deep TCAM to do the match lookup. Each entry has 80x2b sets containing 48 bit MAC address, port number, VLAN Valid/ID, VNI, lookup type (outer or inner packet header). [71:48] bit locations are overloaded for outer vs. inner lookup types. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/t4_regs.h')
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_regs.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index 0971cc41c747..9fea255c7e87 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -2398,6 +2398,30 @@
#define MPS_CLS_TCAM_DATA0_A 0xf000
#define MPS_CLS_TCAM_DATA1_A 0xf004
+#define VIDL_S 16
+#define VIDL_M 0xffffU
+#define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M)
+
+#define DATALKPTYPE_S 10
+#define DATALKPTYPE_M 0x3U
+#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
+
+#define DATAPORTNUM_S 12
+#define DATAPORTNUM_M 0xfU
+#define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M)
+
+#define DATADIPHIT_S 8
+#define DATADIPHIT_V(x) ((x) << DATADIPHIT_S)
+#define DATADIPHIT_F DATADIPHIT_V(1U)
+
+#define DATAVIDH2_S 7
+#define DATAVIDH2_V(x) ((x) << DATAVIDH2_S)
+#define DATAVIDH2_F DATAVIDH2_V(1U)
+
+#define DATAVIDH1_S 0
+#define DATAVIDH1_M 0x7fU
+#define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)
+
#define USED_S 16
#define USED_M 0x7ffU
#define USED_G(x) (((x) >> USED_S) & USED_M)