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| author | Vishal Kulkarni | 2019-02-14 13:49:15 +0100 |
|---|---|---|
| committer | David S. Miller | 2019-02-14 18:39:35 +0100 |
| commit | d429005fdf2c9da19429c8b343eea61bd55b7c00 (patch) | |
| tree | 8d94d8f4c846736890f292bd136df5455d1ac7c2 /drivers/net/ethernet/chelsio/cxgb4/t4_values.h | |
| parent | sfc: Replace dev_kfree_skb_any by dev_consume_skb_any (diff) | |
| download | kernel-qcow2-linux-d429005fdf2c9da19429c8b343eea61bd55b7c00.tar.gz kernel-qcow2-linux-d429005fdf2c9da19429c8b343eea61bd55b7c00.tar.xz kernel-qcow2-linux-d429005fdf2c9da19429c8b343eea61bd55b7c00.zip | |
cxgb4/cxgb4vf: Add support for SGE doorbell queue timer
T6 introduced a Timer Mechanism in SGE called the
SGE Doorbell Queue Timer. With this we can now configure
TX Queues to get CIDX Updates when:
Time(CIDX == PIDX) >= Timer
Previously we rely on TX Queue Status Page updates by hardware
for DMA completions. This will make Hardware/Firmware actually
deliver the CIDX Updates as Ingress Queue messages with
commensurate Interrupts.
So we now have a new RX Path component for processing CIDX Updates
and reclaiming TX Descriptors faster.
Original work by: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Vishal Kulkarni <vishal@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/t4_values.h')
| -rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4/t4_values.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h index f6558cbfc54e..eb1aa82149db 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h @@ -71,12 +71,18 @@ #define FETCHBURSTMIN_64B_X 2 #define FETCHBURSTMIN_128B_X 3 +/* T6 and later use a single-bit encoding for FetchBurstMin */ +#define FETCHBURSTMIN_64B_T6_X 0 +#define FETCHBURSTMIN_128B_T6_X 1 + #define FETCHBURSTMAX_256B_X 2 #define FETCHBURSTMAX_512B_X 3 +#define HOSTFCMODE_INGRESS_QUEUE_X 1 #define HOSTFCMODE_STATUS_PAGE_X 2 #define CIDXFLUSHTHRESH_32_X 5 +#define CIDXFLUSHTHRESH_128_X 7 #define UPDATEDELIVERY_INTERRUPT_X 1 |