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| author | Alexander Duyck | 2012-07-14 08:48:49 +0200 |
|---|---|---|
| committer | Jeff Kirsher | 2012-07-18 22:26:22 +0200 |
| commit | 73079ea0414098ae83f341028434e04d63144ce2 (patch) | |
| tree | 5419e822cd0ae1e3d8eda085d725bccc9fcd1b0b /drivers/net/ethernet/intel/ixgbe/ixgbe.h | |
| parent | ixgbe: Update configure virtualization to allow for multiple PF pools (diff) | |
| download | kernel-qcow2-linux-73079ea0414098ae83f341028434e04d63144ce2.tar.gz kernel-qcow2-linux-73079ea0414098ae83f341028434e04d63144ce2.tar.xz kernel-qcow2-linux-73079ea0414098ae83f341028434e04d63144ce2.zip | |
ixgbe: Add support for SR-IOV w/ DCB or RSS
This change essentially makes it so that we can enable almost all of the
features all at once. This patch allows for the combination of SR-IOV,
DCB, and FCoE in the case of the x540. It also beefs up the SR-IOV by
adding support for RSS to the PF.
The testing matrix gets to be very complex for this patch as there are a
number of different features and subsets for queueing options. I tried to
narrow these down a bit by restricting the PF to only supporting 4TC DCB
when it is enabled in addition to SR-IOV.
Cc: Greg Rose <gregory.v.rose@intel.com>
Cc: John Fastabend <john.r.fastabend@intel.com>
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ixgbe/ixgbe.h')
| -rw-r--r-- | drivers/net/ethernet/intel/ixgbe/ixgbe.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h b/drivers/net/ethernet/intel/ixgbe/ixgbe.h index 5a75a9c8b813..67743aa7acef 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h @@ -284,6 +284,10 @@ struct ixgbe_ring_feature { u16 offset; /* offset to start of feature */ } ____cacheline_internodealigned_in_smp; +#define IXGBE_82599_VMDQ_8Q_MASK 0x78 +#define IXGBE_82599_VMDQ_4Q_MASK 0x7C +#define IXGBE_82599_VMDQ_2Q_MASK 0x7E + /* * FCoE requires that all Rx buffers be over 2200 bytes in length. Since * this is twice the size of a half page we need to double the page order |