summaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
diff options
context:
space:
mode:
authorMoshe Shemesh2019-03-21 23:51:38 +0100
committerSaeed Mahameed2019-03-22 20:09:31 +0100
commite3cfc7e6b7bd59e4ce244deedbad4d1b7a609415 (patch)
treeefbfd7befb33cc09e33ebd71d156011f1e42d9a4 /drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
parentnet/mlx5e: Take SW parser code to a separate function (diff)
downloadkernel-qcow2-linux-e3cfc7e6b7bd59e4ce244deedbad4d1b7a609415.tar.gz
kernel-qcow2-linux-e3cfc7e6b7bd59e4ce244deedbad4d1b7a609415.tar.xz
kernel-qcow2-linux-e3cfc7e6b7bd59e4ce244deedbad4d1b7a609415.zip
net/mlx5e: TX, Add geneve tunnel stateless offload support
Currently support only default geneve udp port (6081). For the tx side, the HW is assisted by SW parsing, which sets the headers offset to offload tunneled LSO and csum. Note that for udp tunnels, we don't use special rx offloads, as rss on the outer headers is enough, we support checksum complete and GRO takes care of aggregation. Geneve TSO BW and CPU load results (tested using iperf single tcp stream). In this patch we add TSO support over Geneve, so the "before" result doesn't actually get to using the TSO HW offload even when turned on. Tested on ConnectX-5, Intel(R) Xeon(R) CPU E5-2660 v2 @2.20GHz. __________________________________ | Before | After | |________________|_________________| | 12.6 Gbits/sec | 21.7 Gbits/sec | | 100% CPU load | 61.5% CPU load | |________________|_________________| Signed-off-by: Moshe Shemesh <moshe@mellanox.com> Acked-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h')
-rw-r--r--drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h51
1 files changed, 51 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
index 1dd225380a66..6da7c88742dc 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
@@ -40,6 +40,57 @@
#include "en_accel/tls_rxtx.h"
#include "en.h"
+#if IS_ENABLED(CONFIG_GENEVE)
+static inline bool mlx5_geneve_tx_allowed(struct mlx5_core_dev *mdev)
+{
+ return mlx5_tx_swp_supported(mdev);
+}
+
+static inline void
+mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
+{
+ struct mlx5e_swp_spec swp_spec = {};
+ unsigned int offset = 0;
+ __be16 l3_proto;
+ u8 l4_proto;
+
+ l3_proto = vlan_get_protocol(skb);
+ switch (l3_proto) {
+ case htons(ETH_P_IP):
+ l4_proto = ip_hdr(skb)->protocol;
+ break;
+ case htons(ETH_P_IPV6):
+ l4_proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
+ break;
+ default:
+ return;
+ }
+
+ if (l4_proto != IPPROTO_UDP ||
+ udp_hdr(skb)->dest != cpu_to_be16(GENEVE_UDP_PORT))
+ return;
+ swp_spec.l3_proto = l3_proto;
+ swp_spec.l4_proto = l4_proto;
+ swp_spec.is_tun = true;
+ if (inner_ip_hdr(skb)->version == 6) {
+ swp_spec.tun_l3_proto = htons(ETH_P_IPV6);
+ swp_spec.tun_l4_proto = inner_ipv6_hdr(skb)->nexthdr;
+ } else {
+ swp_spec.tun_l3_proto = htons(ETH_P_IP);
+ swp_spec.tun_l4_proto = inner_ip_hdr(skb)->protocol;
+ }
+
+ mlx5e_set_eseg_swp(skb, eseg, &swp_spec);
+}
+
+#else
+static inline bool mlx5_geneve_tx_allowed(struct mlx5_core_dev *mdev)
+{
+ return false;
+}
+
+#endif /* CONFIG_GENEVE */
+
static inline void
mlx5e_udp_gso_handle_tx_skb(struct sk_buff *skb)
{