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| author | Saeed Mahameed | 2016-11-28 17:04:50 +0100 |
|---|---|---|
| committer | Saeed Mahameed | 2017-02-06 17:20:16 +0100 |
| commit | 2b31f7ae5f645edd852addfca445895b5806f3f9 (patch) | |
| tree | 89ad451e4ee5255d0a585597812a84d7b6480a2e /drivers/net/ethernet/mellanox/mlx5/core/en_main.c | |
| parent | net/mlx5: Configure cache line size for start and end padding (diff) | |
| download | kernel-qcow2-linux-2b31f7ae5f645edd852addfca445895b5806f3f9.tar.gz kernel-qcow2-linux-2b31f7ae5f645edd852addfca445895b5806f3f9.tar.xz kernel-qcow2-linux-2b31f7ae5f645edd852addfca445895b5806f3f9.zip | |
net/mlx5: TX WQE update
Add new TX WQE fields for Connect-X5 vlan insertion support,
type and vlan_tci, when type = MLX5_ETH_WQE_INSERT_VLAN the
HW will insert the vlan and prio fields (vlan_tci) to the packet.
Those bits and the inline header fields are mutually exclusive, and
valid only when:
MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_NOT_REQUIRED
and MLX5_CAP_ETH(mdev, wqe_vlan_insert),
who will be set in ConnectX-5 and later HW generations.
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en_main.c')
0 files changed, 0 insertions, 0 deletions