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| author | Or Gerlitz | 2018-04-05 14:42:06 +0200 |
|---|---|---|
| committer | Saeed Mahameed | 2018-05-15 00:10:21 +0200 |
| commit | d708f902989b844907c5f7720abe67812a256c33 (patch) | |
| tree | 38c88038ca1fac70bc1be6274ce30075c6d0dc65 /drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | |
| parent | net/mlx5e: Properly order min inline mode setup while parsing TC matches (diff) | |
| download | kernel-qcow2-linux-d708f902989b844907c5f7720abe67812a256c33.tar.gz kernel-qcow2-linux-d708f902989b844907c5f7720abe67812a256c33.tar.xz kernel-qcow2-linux-d708f902989b844907c5f7720abe67812a256c33.zip | |
net/mlx5e: Get the required HW match level while parsing TC flow matches
Introduce levels of matching on headers of offloaded flows
(none, L2, L3, L4) that follow the inline mode levels.
This is pre-step for us to offload flows without any
matches on headers.
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Reviewed-by: Roi Dayan <roid@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/eswitch.h')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index 4cd773fa55e3..efae77dd1e35 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -227,6 +227,13 @@ enum { SET_VLAN_INSERT = BIT(1) }; +enum mlx5_flow_match_level { + MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, + MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, + MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, + MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, +}; + struct mlx5_esw_flow_attr { struct mlx5_eswitch_rep *in_rep; struct mlx5_eswitch_rep *out_rep; |