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| author | Saeed Mahameed | 2018-11-19 19:52:40 +0100 |
|---|---|---|
| committer | Leon Romanovsky | 2018-11-20 19:07:05 +0100 |
| commit | 7701707cb94ed4d1e63ae4fa5ef62a2345ef9db7 (patch) | |
| tree | 8e97e9bfb7b7e2bca454d1170a733b515c33b095 /drivers/net/ethernet/mellanox/mlx5/core/lib | |
| parent | net/mlx5: EQ, Different EQ types (diff) | |
| download | kernel-qcow2-linux-7701707cb94ed4d1e63ae4fa5ef62a2345ef9db7.tar.gz kernel-qcow2-linux-7701707cb94ed4d1e63ae4fa5ef62a2345ef9db7.tar.xz kernel-qcow2-linux-7701707cb94ed4d1e63ae4fa5ef62a2345ef9db7.zip | |
net/mlx5: EQ, Generic EQ
Add mlx5_eq_{create/destroy}_generic APIs and EQE access methods, for
mlx5 core consumers generic EQs.
This API will be used in downstream patch to move page fault (RDMA ODP)
EQ logic into mlx5_ib rdma driver, hence it will use a generic EQ.
Current mlx5 EQ allocation scheme:
On load mlx5 allocates 4 (for async) + #cores (for data completions)
MSIX vectors, mlx5 core will assign 3 MSIX vectors for internal async
EQs and will use all of the #cores MSIX vectors for completion EQs,
(One vector is going to be reserved for a generic EQ).
After this patch an external user (e.g mlx5_ib) of mlx5_core
can use this new API to create new generic EQs with the reserved msix
vector index for that eq.
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Reviewed-by: Leon Romanovsky <leonro@mellanox.com>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/lib')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/lib/eq.h | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/eq.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/eq.h index 706d58383dbd..db32057ad054 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/eq.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/eq.h @@ -7,11 +7,6 @@ #define MLX5_MAX_IRQ_NAME (32) -enum { - MLX5_EQ_MAX_ASYNC_EQS = 4, /* mlx5_core needs at least 3 */ - MLX5_EQ_VEC_COMP_BASE = MLX5_EQ_MAX_ASYNC_EQS, -}; - struct mlx5_eq_tasklet { struct list_head list; struct list_head process_list; @@ -31,6 +26,7 @@ struct mlx5_eq { u32 cons_index; struct mlx5_frag_buf buf; int size; + unsigned int vecidx; unsigned int irqn; u8 eqn; int nent; @@ -44,7 +40,7 @@ struct mlx5_eq_comp { }; struct mlx5_eq_pagefault { - struct mlx5_eq core; /* Must be first */ + struct mlx5_eq *core; struct work_struct work; spinlock_t lock; /* Pagefaults spinlock */ struct workqueue_struct *wq; @@ -55,10 +51,6 @@ int mlx5_eq_table_init(struct mlx5_core_dev *dev); void mlx5_eq_table_cleanup(struct mlx5_core_dev *dev); int mlx5_eq_table_create(struct mlx5_core_dev *dev); void mlx5_eq_table_destroy(struct mlx5_core_dev *dev); -int mlx5_create_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, - int nent, u64 mask, const char *name, - irq_handler_t handler); -int mlx5_destroy_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq); int mlx5_eq_del_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq); |