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| author | Feras Daoud | 2018-11-12 14:23:02 +0100 |
|---|---|---|
| committer | Saeed Mahameed | 2019-06-13 22:23:17 +0200 |
| commit | 63cbc552eebf08818af2025aef4589a48ef849c0 (patch) | |
| tree | 5c73ca2206d8ca93d4eb88d2425bfc3ce9788764 /drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | |
| parent | net/mlx5: Add Crdump support (diff) | |
| download | kernel-qcow2-linux-63cbc552eebf08818af2025aef4589a48ef849c0.tar.gz kernel-qcow2-linux-63cbc552eebf08818af2025aef4589a48ef849c0.tar.xz kernel-qcow2-linux-63cbc552eebf08818af2025aef4589a48ef849c0.zip | |
net/mlx5: Handle SW reset of FW in error flow
New mlx5 adapters allow the driver to reset the FW in the event of an
error, this action called "SW Reset". When an SW reset is issued on any
PF all PFs enter reset state which is a recoverable condition. The
existing recovery flow was designed to allow the recovery of a VF after
a PF driver reload. This patch adds the sw reset to the NIC states
as a preparation for sw reset handling.
When a software reset is issued the following occurs:
1. The NIC interface mode is set to 7 while the reset is in progress.
2. Once the reset completes the NIC interface mode is set to 1.
Signed-off-by: Feras Daoud <ferasda@mellanox.com>
Signed-off-by: Moshe Shemesh <moshe@mellanox.com>
Signed-off-by: Daniel Jurgens <danielj@mellanox.com>
Reviewed-by: Alex Vesker <valex@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index d4dd8c1ae55c..97f8cf67ced0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -214,7 +214,7 @@ enum { MLX5_NIC_IFC_FULL = 0, MLX5_NIC_IFC_DISABLED = 1, MLX5_NIC_IFC_NO_DRAM_NIC = 2, - MLX5_NIC_IFC_INVALID = 3 + MLX5_NIC_IFC_SW_RESET = 7 }; u8 mlx5_get_nic_state(struct mlx5_core_dev *dev); |