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| author | Daniel Pieczko | 2014-04-01 14:10:34 +0200 |
|---|---|---|
| committer | David S. Miller | 2014-04-01 22:25:51 +0200 |
| commit | 52ad762b85ed7947ec9eff6b036eb985352f6874 (patch) | |
| tree | eeb702d106b39d7eea57cbd425713f2767ba319b /drivers/net/ethernet/sfc/ef10.c | |
| parent | xen-netback: disable rogue vif in kthread context (diff) | |
| download | kernel-qcow2-linux-52ad762b85ed7947ec9eff6b036eb985352f6874.tar.gz kernel-qcow2-linux-52ad762b85ed7947ec9eff6b036eb985352f6874.tar.xz kernel-qcow2-linux-52ad762b85ed7947ec9eff6b036eb985352f6874.zip | |
Call efx_set_channels() before efx->type->dimension_resources()
When using the "separate_tx_channels=1" module parameter, the TX queues are
initially numbered starting from the first TX-only channel number (after all the
RX-only channels). efx_set_channels() renumbers the queues so that they are
indexed from zero.
On EF10, the TX queues need to be relabelled in this way before calling the
dimension_resources NIC type operation, otherwise the TX queue PIO buffers can be
linked to the wrong VIs when using "separate_tx_channels=1".
Added comments to explain UC/WC mappings for PIO buffers
Signed-off-by: Shradha Shah <sshah@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/sfc/ef10.c')
| -rw-r--r-- | drivers/net/ethernet/sfc/ef10.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ethernet/sfc/ef10.c b/drivers/net/ethernet/sfc/ef10.c index 651626e133f9..21c20ea0dad0 100644 --- a/drivers/net/ethernet/sfc/ef10.c +++ b/drivers/net/ethernet/sfc/ef10.c @@ -565,10 +565,17 @@ static int efx_ef10_dimension_resources(struct efx_nic *efx) * several of each (in fact that's the only option if host * page size is >4K). So we may allocate some extra VIs just * for writing PIO buffers through. + * + * The UC mapping contains (min_vis - 1) complete VIs and the + * first half of the next VI. Then the WC mapping begins with + * the second half of this last VI. */ uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF); if (nic_data->n_piobufs) { + /* pio_write_vi_base rounds down to give the number of complete + * VIs inside the UC mapping. + */ pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + nic_data->n_piobufs) * |