diff options
| author | Alan Liu | 2017-12-22 14:39:32 +0100 |
|---|---|---|
| committer | Kalle Valo | 2017-12-27 11:20:41 +0100 |
| commit | 703f261dd77f3afb8058a927ca2f4651691f0495 (patch) | |
| tree | a9dfff4df47885fbb0a4ec423ea05a34d0b500ec /drivers/net/wireless/ath/ath10k/hw.h | |
| parent | ath10k: add coredump_mask module parameter (diff) | |
| download | kernel-qcow2-linux-703f261dd77f3afb8058a927ca2f4651691f0495.tar.gz kernel-qcow2-linux-703f261dd77f3afb8058a927ca2f4651691f0495.tar.xz kernel-qcow2-linux-703f261dd77f3afb8058a927ca2f4651691f0495.zip | |
ath10k: add memory dump support for QCA6174/QCA9377
Add memory dump to the firmware crash data file which is provided to user space
via devcoredump interface. This makes it easier for firmware engineers to debug
firmware crashes.
Due to increased memory consumption the memory dump is disabled by default. To
enable it make sure that bit 3 is set in coredump_mask module parameter:
modprobe ath10k_core coredump_mask=0xffffffff
When RAMDUMP is enabled a buffer for the dump is allocated with vmalloc during
device probe. The actual memory layout is different in hardware versions and
the layouts are defined in coredump.c. The memory is split to regions and, to
get even finegrained control of what to copy, the region can split to smaller
sections as not all registers are readable (which could cause the whole system
to stall).
Signed-off-by: Alan Liu <alanliu@qca.qualcomm.com>
[kvalo@qca.qualcomm.com: refactoring and cleanup]
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath10k/hw.h')
| -rw-r--r-- | drivers/net/wireless/ath/ath10k/hw.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h index 84aedaa95f84..2bd70a551557 100644 --- a/drivers/net/wireless/ath/ath10k/hw.h +++ b/drivers/net/wireless/ath/ath10k/hw.h @@ -888,6 +888,7 @@ ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address #define CPU_INTR_ADDRESS 0x0010 +#define FW_RAM_CONFIG_ADDRESS 0x0018 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) |