ath9k_hw: add AR9580 support

Here are the AR9580 1.0 initvals checksums using the
Atheros initvals-tools [1]. This is useful for when
we udate the initvals again with other values. It ensures
that we match the same initvals used internally. The
tool is documented on the wiki [2].

$ ./initvals -f ar9580-1p0
0x00000000e912711f        ar9580_1p0_modes_fast_clock
0x000000004a488fc7        ar9580_1p0_radio_postamble
0x00000000f3888b02        ar9580_1p0_baseband_core
0x0000000003f783bb        ar9580_1p0_mac_postamble
0x0000000094be244a        ar9580_1p0_low_ob_db_tx_gain_table
0x0000000094be244a        ar9580_1p0_high_power_tx_gain_table
0x0000000090be244a        ar9580_1p0_lowest_ob_db_tx_gain_table
0x00000000ed9eaac6        ar9580_1p0_baseband_core_txfir_coeff_japan_2484
0x00000000c4d66d1b        ar9580_1p0_mac_core
0x00000000e8e9043a        ar9580_1p0_mixed_ob_db_tx_gain_table
0x000000003521a300        ar9580_1p0_wo_xlna_rx_gain_table
0x00000000301fc841        ar9580_1p0_soc_postamble
0x00000000a9a06b3a        ar9580_1p0_high_ob_db_tx_gain_table
0x00000000a15ccf1b        ar9580_1p0_soc_preamble
0x0000000029495000        ar9580_1p0_rx_gain_table
0x0000000037ac0ee8        ar9580_1p0_radio_core
0x00000000603a1b80        ar9580_1p0_baseband_postamble
0x000000003d8b4396        ar9580_1p0_pcie_phy_clkreq_enable_L1
0x00000000398b4396        ar9580_1p0_pcie_phy_clkreq_disable_L1
0x00000000397b4396        ar9580_1p0_pcie_phy_pll_on_clkreq

[1] git://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/initvals-tool.git
[2] http://wireless.kernel.org/en/users/Drivers/ath9k_hw/initvals-tool

Cc: David Quan <dquan@qca.qualcomm.com>
Cc: Kathy Giori <kgiori@qca.qualcomm.com>
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Tested-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 81 insertions, 0 deletions

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 9cf5d13529c2..b6839e695270 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -21,6 +21,7 @@
 #include "ar9340_initvals.h"
 #include "ar9330_1p1_initvals.h"
 #include "ar9330_1p2_initvals.h"
+#include "ar9580_1p0_initvals.h"
 
 /* General hardware code for the AR9003 hadware family */
 
@@ -253,6 +254,56 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 				ar9485_1_1_pcie_phy_clkreq_disable_L1,
 				ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 				2);
+	} else if (AR_SREV_9580(ah)) {
+		/* mac */
+		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+				ar9580_1p0_mac_core,
+				ARRAY_SIZE(ar9580_1p0_mac_core), 2);
+		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+				ar9580_1p0_mac_postamble,
+				ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
+
+		/* bb */
+		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+				ar9580_1p0_baseband_core,
+				ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
+		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+				ar9580_1p0_baseband_postamble,
+				ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
+
+		/* radio */
+		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+				ar9580_1p0_radio_core,
+				ARRAY_SIZE(ar9580_1p0_radio_core), 2);
+		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+				ar9580_1p0_radio_postamble,
+				ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
+
+		/* soc */
+		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+				ar9580_1p0_soc_preamble,
+				ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
+		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+				ar9580_1p0_soc_postamble,
+				ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
+
+		/* rx/tx gain */
+		INIT_INI_ARRAY(&ah->iniModesRxGain,
+				ar9580_1p0_rx_gain_table,
+				ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
+		INIT_INI_ARRAY(&ah->iniModesTxGain,
+				ar9580_1p0_low_ob_db_tx_gain_table,
+				ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
+				5);
+
+		INIT_INI_ARRAY(&ah->iniModesAdditional,
+				ar9580_1p0_modes_fast_clock,
+				ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
+				3);
 	} else {
 		/* mac */
 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -348,6 +399,11 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 				       ar9485_modes_lowest_ob_db_tx_gain_1_1,
 				       ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 				       5);
+		else if (AR_SREV_9580(ah))
+			INIT_INI_ARRAY(&ah->iniModesTxGain,
+			      ar9580_1p0_lowest_ob_db_tx_gain_table,
+			      ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
+			      5);
 		else
 			INIT_INI_ARRAY(&ah->iniModesTxGain,
 				       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
@@ -375,6 +431,11 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 				       ar9485Modes_high_ob_db_tx_gain_1_1,
 				       ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
 				       5);
+		else if (AR_SREV_9580(ah))
+			INIT_INI_ARRAY(&ah->iniModesTxGain,
+				ar9580_1p0_high_ob_db_tx_gain_table,
+				ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
+				       5);
 		else
 			INIT_INI_ARRAY(&ah->iniModesTxGain,
 				       ar9300Modes_high_ob_db_tx_gain_table_2p2,
@@ -402,6 +463,11 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 				       ar9485Modes_low_ob_db_tx_gain_1_1,
 				       ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
 				       5);
+		else if (AR_SREV_9580(ah))
+			INIT_INI_ARRAY(&ah->iniModesTxGain,
+				 ar9580_1p0_low_ob_db_tx_gain_table,
+				 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
+				 5);
 		else
 			INIT_INI_ARRAY(&ah->iniModesTxGain,
 				       ar9300Modes_low_ob_db_tx_gain_table_2p2,
@@ -429,6 +495,11 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 				       ar9485Modes_high_power_tx_gain_1_1,
 				       ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
 				       5);
+		else if (AR_SREV_9580(ah))
+			INIT_INI_ARRAY(&ah->iniModesTxGain,
+				ar9580_1p0_high_power_tx_gain_table,
+				ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
+				5);
 		else
 			INIT_INI_ARRAY(&ah->iniModesTxGain,
 				       ar9300Modes_high_power_tx_gain_table_2p2,
@@ -463,6 +534,11 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 				       ar9485Common_wo_xlna_rx_gain_1_1,
 				       ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 				       2);
+		else if (AR_SREV_9580(ah))
+			INIT_INI_ARRAY(&ah->iniModesRxGain,
+				       ar9580_1p0_rx_gain_table,
+				       ARRAY_SIZE(ar9580_1p0_rx_gain_table),
+				       2);
 		else
 			INIT_INI_ARRAY(&ah->iniModesRxGain,
 				       ar9300Common_rx_gain_table_2p2,
@@ -490,6 +566,11 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 				       ar9485Common_wo_xlna_rx_gain_1_1,
 				       ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 				       2);
+		else if (AR_SREV_9580(ah))
+			INIT_INI_ARRAY(&ah->iniModesRxGain,
+				   ar9580_1p0_wo_xlna_rx_gain_table,
+				   ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
+				   2);
 		else
 			INIT_INI_ARRAY(&ah->iniModesRxGain,
 				       ar9300Common_wo_xlna_rx_gain_table_2p2,