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| author | Niklas Cassel | 2017-12-20 00:29:36 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi | 2017-12-21 12:10:34 +0100 |
| commit | b6900aeb1977ee1430578ce8b373e5c9fc6366d5 (patch) | |
| tree | 369ac88c88bbb68309043e6066095d2ba5a65495 /drivers/pci/dwc/pcie-artpec6.c | |
| parent | PCI: dwc: artpec6: Add support for endpoint mode (diff) | |
| download | kernel-qcow2-linux-b6900aeb1977ee1430578ce8b373e5c9fc6366d5.tar.gz kernel-qcow2-linux-b6900aeb1977ee1430578ce8b373e5c9fc6366d5.tar.xz kernel-qcow2-linux-b6900aeb1977ee1430578ce8b373e5c9fc6366d5.zip | |
PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument
The current cpu addr fixup mask for ARTPEC-6, GENMASK(27, 0), is wrong.
The correct cpu addr fixup mask for ARTPEC-6 is GENMASK(28, 0).
However, having a hardcoded cpu addr fixup mask in each driver is
arguably wrong.
A device tree property called something like "cpu-addr-fixup-mask"
would have been a better solution.
Introducing such a property is not needed though, since we already have
pp->cfg0_base and ep->phys_base, which is derived from already existing
device tree properties.
It is also worth noting that for ARTPEC-7, hardcoding the cpu addr fixup
mask is not possible, since it uses a High Address Bits Look Up Table,
which means that it can, at runtime, map the PCIe window to an arbitrary
address in the 32-bit address space.
By using pp->cfg0_base and ep->phys_base, we avoid hardcoding a mask
in each driver. This should work for ARTPEC-6, DRA7xx, and ARTPEC-7.
I have not changed the code in DRA7xx though, since their existing
code works, but if they want, they could use the same logic as
artpec6_pcie_cpu_addr_fixup, and thus remove their hardcoded mask.
The reason why the fixup mask is needed is explained in commit f4c55c5a3f7f
("PCI: designware: Program ATU with untranslated address").
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/pci/dwc/pcie-artpec6.c')
| -rw-r--r-- | drivers/pci/dwc/pcie-artpec6.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c index e7de4e4649eb..318a2bd0d97e 100644 --- a/drivers/pci/dwc/pcie-artpec6.c +++ b/drivers/pci/dwc/pcie-artpec6.c @@ -67,8 +67,6 @@ static const struct of_device_id artpec6_pcie_of_match[]; #define PHY_STATUS 0x118 #define PHY_COSPLLLOCK BIT(0) -#define ARTPEC6_CPU_TO_BUS_ADDR GENMASK(27, 0) - static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset) { u32 val; @@ -82,9 +80,21 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u regmap_write(artpec6_pcie->regmap, offset, val); } -static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr) +static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr) { - return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR; + struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci); + struct pcie_port *pp = &pci->pp; + struct dw_pcie_ep *ep = &pci->ep; + + switch (artpec6_pcie->mode) { + case DW_PCIE_RC_TYPE: + return pci_addr - pp->cfg0_base; + case DW_PCIE_EP_TYPE: + return pci_addr - ep->phys_base; + default: + dev_err(pci->dev, "UNKNOWN device type\n"); + } + return pci_addr; } static int artpec6_pcie_establish_link(struct dw_pcie *pci) |